Description: 高精度乘法基本思想和加法一样。其基本流程如下：
①读入被乘数s1，乘数s2
②把s1、s2分成4位一段，转成数值存在数组a,b中；记下a,b的长度k1,k2；
③i赋为b中的最低位；
④从b中取出第i位与a相乘，累加到另一数组c中；（注意：累加时错开的位数应是多少位
？）
⑤i:=i-1；检测i值：小于k2则转⑥,否则转④
⑥打印结果-High-precision multiplication and addition the same basic idea. The basic process is as follows: ① read multiplicand s1, multiplier s2 ② to s1, s2 is divided into four section into the existence of an array of values a, b in write down a, b the length of k1, k2 ③ i given for the b of the lowest ④ Remove from b in the first i-bit and a multiply, accumulate to another array in c (Note: The median cumulative time should be staggered how many?) ⑤ i: = i-1 detection i value: less than k2 was transferred ⑥, otherwise switch to print the results ④ ⑥ Platform: |
Size: 1024 |
Author:Eurik |
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Description: 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用)
-With the VHDL language to describe the design and realization of multiplier-accumulator, four of multiplicand X and 4-bit multiplier Y input, the temporary 4-bit registers in the register A and B, registers A and B multiplied by the output of the first, to be 8-bit product, the product further with the 8-bit output of register C, the sum of, the sum of the results stored in register C,. The output register C is also the system output Z. (Original, which are multiply and accumulate some part may be raised separately, very good use) Platform: |
Size: 967680 |
Author:jlz |
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Description: 一个简易计算器，用单片机实现。可以实现加、减、乘、除，累加等简易运算。用以学习之用-A simple calculator, with MCU. Can add, subtract, multiply, divide, accumulate and other simple operations. Used to study Platform: |
Size: 48128 |
Author:lvyan |
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Description: this file is a multiply and accumulate logic built in VHDL platform.-this file is a multiply and accumulate logic built in VHDL platform. Platform: |
Size: 2048 |
Author:varun konda |
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Description: 有一组16个数，分别统计负数、0、正数的个数，并将结果保存number
area reset,data,readwrite
source dcb 1,2,5,-6,-5,3,0,7,-9,0,0,5,12,-94,-3,55
number dcb 0,0,0 分别保存统计得到的 负数，0，正数的个数
对数据区进行64位结果累加操作
先对内存地址0x3000开始的100个字内存单元填入0x10000001~0x10000064字数据，然后将每个字单元进行64位累加结果保存于【r9:r8】中（r9中存放高32位）。
先通过循环对内存单元进行赋值，再将100个字进行累加。
求一个数的阶乘（64位结果）
用ARM汇编语言程序设计实现求20！（20的阶乘），并将其64位结果放在【r9:r8】中（r9中存放高32位）。
设计思路：64位结果的乘法指令通过两个32位寄存器相乘，可以得到64位结果，在每次循环相乘中，可以将存放64位结果的两个寄存器分别与递增量相乘，最后将得到的高32位结果相加。-There is a group number 16, respectively Statistics negative, zero, positive number, and save the result number
area reset, data, readwrite
source dcb 1,2,5,-6,-5,3,0,7,-9,0,0,5,12,-94,-3,55
number dcb 0,0,0 were preserved statistics obtained negative, 0, the number of positive numbers
For data area 64 cumulative operating result
First memory unit of 100 words began to fill the memory address 0x3000 0x10000001 ~ 0x10000064 word data, and then each word unit 64 cumulative result is saved in [r9: r8] in (r9 stored in the high 32).
First through the loop on the memory unit assignment, then 100 words accumulate.
Seeking a number of factorial (64 results)
ARM assembly language programming seeking to achieve 20! (Factorial 20), and 64 results in [r9: r8] in (r9 stored in the high 32).
Design ideas: 64 results multiply instruction is multiplied by two 32-bit registers, you can get 64 results in multiplying each cycle, you c Platform: |
Size: 472064 |
Author:杜瑜瑜 |
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Description: 采用一种基于FPGA的IIR数字滤波器的设计方案,通过QuartusⅡ的设计平台，采用自顶向下的模块化设计思想将整个IIR数字滤波器分为：时序控制、延时、补码乘加和累加四个功能模块。分别对各模块采用VHDL进行描述后，进行了仿真和综合。-IIR digital filter using a FPGA-based design, analyzes the theory and design method of IIR digital filter, then through QuartusⅡ design platform, using a top-down modular design the entire IIR digital filter divided into: timing control, delay, complement multiply and accumulate four functional modules. Respectively, after each module using VHDL description, simulation and synthesis. Platform: |
Size: 3625984 |
Author:wangqian |
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