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[Other] leon3-memec-v2mb1000

Description: LEON3 SOC GRlip IP core. Memory controller.-LEON3 GRlip SOC IP core. Memory controller.
Platform: | Size: 104270 | Author: 岳昆 | Hits:

[Other] leon3-clock-gate

Description: Clock gating logic for LEON3 processor.
Platform: | Size: 114700 | Author: 岳昆 | Hits:

[Other] leon3-altera-ep1c20

Description: leon3 patch for altera ep1c20 FPGA.
Platform: | Size: 101026 | Author: 岳昆 | Hits:

[Other resource] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114780 | Author: king.xia | Hits:

[SourceCode] leon3 debug

Description: 基于leon3的debugger，采用最新的方法进行debugger的设计，是一种新的思路
Platform: | Size: 938 | Author: 874132129@qq.com | Hits:

[ARM-PowerPC-ColdFire-MIPS] leon3

Description: sun公司的sparc v8处理器的配置代码。-the sun sparc ET processor configuration code.
Platform: | Size: 43008 | Author: 吴明诗 | Hits:

[Other] leon3-altera-ep2s60-ddr

Description: The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.-The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) developmen t. The IP cores are centered around a common on-c hip bus, and use a coherent method for simulation and syn thesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug
Platform: | Size: 103424 | Author: 岳昆 | Hits:

[Other] leon3-memec-v2mb1000

Description: LEON3 SOC GRlip IP core. Memory controller.-LEON3 GRlip SOC IP core. Memory controller.
Platform: | Size: 104448 | Author: 岳昆 | Hits:

[Other] leon3-clock-gate

Description: Clock gating logic for LEON3 processor.
Platform: | Size: 114688 | Author: 岳昆 | Hits:

[Other] leon3-altera-ep1c20

Description: leon3 patch for altera ep1c20 FPGA.
Platform: | Size: 101376 | Author: 岳昆 | Hits:

[Other] leon3_pci

Description: LEON3 SOC environment, PCI bridges.
Platform: | Size: 71680 | Author: 岳昆 | Hits:

[MiddleWare] leon3-altera-ep2s60-sdr

Description: ahb sdram interface.arm cpu series,include controller
Platform: | Size: 98304 | Author: | Hits:

[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114688 | Author: | Hits:

[VHDL-FPGA-Verilog] cpu-leon3-altera-ep1c20

Description: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了在Altera公司的ep1c20 FPGA的位码文件和配置文件，可以直接下载使用！-A VHDL design with the use of powerful 32-bit CPU, this document contains Altera Corporation in the ep1c20 FPGA code and configuration files, you can direct download!
Platform: | Size: 687104 | Author: zhao onely | Hits:

[VHDL-FPGA-Verilog] cpu-leon3-altera-ep2s60-ddr

Description: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
Platform: | Size: 752640 | Author: zhao onely | Hits:

[VHDL-FPGA-Verilog] cpu-leon3-xilinx-ml505

Description:
Platform: | Size: 391168 | Author: zhao onely | Hits:

[VHDL-FPGA-Verilog] leon3

Description: leon3 source code 虽然gaisler网站上有下载，但是提供此代码，希望能与更多的朋友一起学习leon-leon3 source code although gaisler website to download, but the provision of this code, would like to work with more friends with learning leon
Platform: | Size: 144384 | Author: CGF | Hits:

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[Other] leon3-memec-v2mb1000

[Other] leon3-clock-gate

[Other] leon3-altera-ep1c20

[Other resource] leon3-altera-ep2s60-ddr

[SourceCode] leon3 debug

[ARM-PowerPC-ColdFire-MIPS] leon3

[Other] leon3-altera-ep2s60-ddr

[Other] leon3-memec-v2mb1000

[Other] leon3-clock-gate

[Other] leon3-altera-ep1c20

[Other] leon3_pci

[MiddleWare] leon3-altera-ep2s60-sdr

[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr

[VHDL-FPGA-Verilog] cpu-leon3-altera-ep1c20

[VHDL-FPGA-Verilog] cpu-leon3-altera-ep2s60-ddr

[VHDL-FPGA-Verilog] cpu-leon3-xilinx-ml505

[VHDL-FPGA-Verilog] leon3

[VHDL-FPGA-Verilog] leon3

[VHDL-FPGA-Verilog] LEON3

[VHDL-FPGA-Verilog] LEON3

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