Search - I2C IP master

[VHDL-FPGA-Verilog] i2c_slave_model_verilog

Description: 一般网站上都有i2c master模块的代码,但很少有slave的代码,这里就是slave的代码,非常有用.-general website have i2c master module of code, but very few slave code, This is the slave code, very useful.
Platform: | Size: 2048 | Author: hxwf801 | Hits:

[VC/MFC] altera_avalon_i2c

Description: i2c IP核 i2c.master i2c.mater.v-i2c IP core
Platform: | Size: 181248 | Author: zhengzhiqiang | Hits:

[VHDL-FPGA-Verilog] i2c_master_slave_core

Description: I2C master/slave IP core
Platform: | Size: 2180096 | Author: zhanglh | Hits:

[Other] i2c

Description: i2c master controller, free ip
Platform: | Size: 11264 | Author: lai | Hits:

[VHDL-FPGA-Verilog] I2C_code

Description: 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
Platform: | Size: 3256320 | Author: summerooooo | Hits:

[VHDL-FPGA-Verilog] RD1054

Description: i2c接口的master ip 适用于lattice的器件-i2c master ip interface device for lattice
Platform: | Size: 620544 | Author: y | Hits:

[Other] i2c_master

Description: I2C master模式的IP core（verilog）-I2C master mode IP core (verilog)
Platform: | Size: 4096 | Author: Liu Zhao | Hits:

[VHDL-FPGA-Verilog] i2c

Description: I2C master mode IP core
Platform: | Size: 276480 | Author: Liu Zhao | Hits:

[VHDL-FPGA-Verilog] i2c_core

Description: i2c ip core support slave and master mode
Platform: | Size: 1251328 | Author: bell | Hits:

[VHDL-FPGA-Verilog] i2c_verilog

Description: I2C Master IP 核 I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance between many devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. -I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance between many devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. The interface defines 3 transmission speeds: - Normal: 100Kbps - Fast: 400Kbps - High speed: 3.5Mbps Only 100Kbps and 400Kbps modes are supported directly. For High speed special IOs are needed. If these IOs are available and used, then High speed is also supported.
Platform: | Size: 11264 | Author: qingmingyang | Hits:

[VHDL-FPGA-Verilog] i2c_master_slave_core

Description: I2C接口的主从模式代码,独立的IP，可以快速嵌入到自己的设计项目！-Master I2C interface code from the model, independent of IP, you can quickly embed into their design projects!
Platform: | Size: 1262592 | Author: 乔铁宏 | Hits:

[VHDL-FPGA-Verilog] i2c-master

Description: i2c 总线 host 控制器， fpga上验证过，可以实现i2c 通信。-verilog IP for i2c master controller
Platform: | Size: 978944 | Author: guoqingsheng | Hits:

[Software Engineering] DX81-FILES11

Description: 防抄板、物联网安全、IP保护等解决方案 DX安全加密芯片： DX81C04：  防抄板认证  加密EEPROM存储  密钥存储、认证  设备认证 DX82C04：  防抄板认证  加密EEPROM存储  密钥存储、认证  设备认证  动态密钥产生  实时数据加密老板、程序员、烧录工人三者文件隔离；密钥老板自己掌握标准I2C，可以挂多个设备，非独占；数据线动态随机访问；我们正在设计的DX83/4系列对应ATECC108 (ECC算法）关键是技术支持，atmel/maxim等芯片的资料很不完善，特别是对于没有使用过的工程师来说，开发难度大。我们承诺，协助工程师一天内调试好DX加密芯片。加密芯片功能总结： 1.防抄板（对换加密芯片，对换flash都工作不了） 2.加密存储（重要参数，算法参数等密文存储） 3.设备认证（防伪认证） 4.密文传输（用DX82) 恒泰瑞科技 13128806959-Anti-copy board, networking security, IP protection and other security encryption chip solutions DX: DX81C04:  anti-copy board certification   encrypted EEPROM memory key storage, authentication  device authentication DX82C04:  anti-copy board certified encryption EEPROM memory   key storage, authentication device authentication    dynamic real-time data encryption key generation owners, programmers, workers burn the three file quarantine key boss master standard I2C, you can hang multiple devices, non-exclusive dynamic data lines random access we are designed DX83/4 series correspond ATECC108 (ECC algorithm) is a key technical support, the chip information atmel/maxim, etc. is not perfect, especially for engineers who have not used, development is difficult. We are committed to help engineers debug the day DX encryption chip. Encryption chip features summary: 1. The anti-copy board (for encryption chip
Platform: | Size: 8929280 | Author: 陈迪勇 | Hits:

[VHDL-FPGA-Verilog] i2c_master_ip_for_nios

Description: i2c master ip for altera nios, add in qsys
Platform: | Size: 218112 | Author: kevinfeng83 | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] i2c_slave_model_verilog

[VC/MFC] altera_avalon_i2c

[VHDL-FPGA-Verilog] i2c_master_slave_core

[Other] i2c

[VHDL-FPGA-Verilog] I2C_code

[VHDL-FPGA-Verilog] RD1054

[Other] i2c_master

[VHDL-FPGA-Verilog] i2c

[VHDL-FPGA-Verilog] i2c_core

[VHDL-FPGA-Verilog] i2c_verilog

[VHDL-FPGA-Verilog] i2c_master_slave_core

[VHDL-FPGA-Verilog] i2c-master

[Software Engineering] DX81-FILES11

[VHDL-FPGA-Verilog] i2c_master_ip_for_nios

CodeBus www.codebus.net