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Description: 电源：稳压的＋5V电源，电流小于300mA。
视频输入：RGB＋HSYNC＋VSYNC信号，取自VGA卡，刷新率与NTSC标准兼容。
视频输出：混合视频和S－视频（Y/C）。
支持的视频标准：PAL B、G、H和NTSCM。
电路要求VGA卡能发送与PAL或NTSC标准视频时序兼容的RGB格式视频信号。
Platform: |
Size: 32579 |
Author: modayong |
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Description: 电源：稳压的＋5V电源，电流小于300mA。
视频输入：RGB＋HSYNC＋VSYNC信号，取自VGA卡，刷新率与NTSC标准兼容。
视频输出：混合视频和S－视频（Y/C）。
支持的视频标准：PAL B、G、H和NTSCM。
电路要求VGA卡能发送与PAL或NTSC标准视频时序兼容的RGB格式视频信号。
-Power: 5 V regulated power supply current of less than 300mA. Video input: RGB HSYNC VSYNC signals from the VGA card, refresh rate compatible with the NTSC standard. Video Output: Mixed video and S-video (Y/C). Supported video standards: PAL B, G, H and NTSCM. Circuit requirements of VGA cards can be sent with the PAL or NTSC standard video timing compatible RGB format video signals.
Platform: |
Size: 32768 |
Author: |
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Description: verilog文件 实现VGA时序驱动，产生vsync和hsync信号。附有自检测程序。-Verilog file to achieve VGA timing-driven, resulting in VSYNC and HSYNC signals. With self-testing procedures.
Platform: |
Size: 3072 |
Author: summer |
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Description: 从fpga到vga输出的verilog程序，信号包括了RGB,VSYNC,HSYNC信号！-the program in verilog from fpga to vga ,which includes the signal of red\green\blue and vsync\hsync.
Platform: |
Size: 2048 |
Author: zyc |
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Description: 实现vga的实现odule VGA(
clock,
switch,
disp_RGB,
hsync,
vsync
)
input clock //系统输入时钟 50MHz
input [1:0]switch
output [2:0]disp_RGB //VGA数据输出
output hsync //VGA行同步信号
output vsync //VGA场同步信号
reg [9:0] hcount //VGA行扫描计数器
reg [9:0] vcount //VGA场扫描计数器
reg [2:0] data
reg [2:0] h_dat
reg [2:0] v_dat
//reg [9:0] timer
reg flag
wire hcount_ov
wire vcount_ov
wire dat_act
wire hsync
wire vsync
reg vga_clk
//VGA行、场扫描时序参数表-Vga achieve the realization odule VGA (clock, switch, disp_RGB, hsync, vsync) input clock // system input clock 50MHz input [1:0] switch output [2:0] disp_RGB // VGA output hsync data output // VGA horizontal synchronization signal output vsync // VGA vertical sync signals reg [9:0] hcount // VGA line scan counter reg [9:0] vcount // VGA-field scanning counter reg [2:0] data reg [2:0] h_dat reg [2:0] v_dat // reg [9:0] timer reg flag wire hcount_ov wire vcount_ov wire dat_act wire hsync wire vsync reg vga_clk // VGA horizontal and vertical scanning Timing Parameters Table
Platform: |
Size: 45056 |
Author: 李阳 |
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Description: verilog文件 实现VGA时序驱动，产生vsync和hsync信号。附有自检测程序。-Verilog file to achieve VGA timing-driven, resulting in VSYNC and HSYNC signals. With self-testing procedures.
Platform: |
Size: 4096 |
Author: asacoup |
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Description: Description : Modify CRT1 Hsync Vsync to fix LCD mode timing.
Platform: |
Size: 24576 |
Author: riqairv |
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Description: Image processing - LV to HSYNC and VSYNC
Platform: |
Size: 1024 |
Author: Miracle |
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