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[Other resource] seven_segment

Description: 以QuatusⅡ为平台，用HVDL语言实现7段数码管译码器的功能。
Platform: | Size: 101341 | Author: cheng sonja | Hits:

[SCM] seven_segment

Description: 以QuatusⅡ为平台，用HVDL语言实现7段数码管译码器的功能。-Quatus Ⅱ as a platform to use language to achieve HVDL digital tube 7 decoder functions.
Platform: | Size: 101376 | Author: cheng sonja | Hits:

[VHDL-FPGA-Verilog] VHDL-Handbook

Description: VHDL handbook is very nice and suitable guide to HVDL language
Platform: | Size: 1343488 | Author: stdominic | Hits:

[VHDL-FPGA-Verilog] cof

Description: 咖啡机的基本设计，是HVDL语言描写的，用于基本的咖啡机控制-cafe
Platform: | Size: 1024 | Author: sara | Hits:

[VHDL-FPGA-Verilog] hvdl

Description: 实现60秒秒表功能，代码简单，可扩展，可操作，已在FPGA开发板上实现-Achieve 60 seconds stopwatch function, the code is simple, scalable, operable in FPGA development board to achieve
Platform: | Size: 1024 | Author: gong | Hits:

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