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Description: 帧同步模块的Veriolog源码。
在ModelSim下的一个工程。有测试文件。-frame synchronization module Veriolog source. The ModelSim of a project. A test document.
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Size: 24576 |
Author: 刘仪 |
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Description: 本设计采用Cypress公司支持USB2.0协议标准的EZ-USB FX2系列之CY7C68013芯片作为帧同步信号发送器的USB接口芯片，在uVision2开发环境下利用Keil C51完成了满足帧同步信号发送器基本要求的固件设计，具体采用了批量传输方式、大端点三缓冲设置、定时器中断方式的同步脉冲和数据的发送、软FIFO方式数据存放以及I2C总线下的LED显示等技术，最后协助编写USB底层驱动程序实现了固件自动下载。经过测试，所设计的帧同步信号发送器基本达到了课题所要求的基本原理性设计与验证。
-This design uses Cypress supports USB2.0 protocol standards of EZ-USB FX2 Series CY7C68013 chip as a frame synchronization signal transmitter of the USB interface chip, in uVision2 development environment using Keil C51 completed a frame synchronization signal to meet the basic requirements of transmitter firmware design, specific use of a bulk transfer mode, the endpoint buffer three settings, the timer interrupt the sync pulse and data transmission, soft FIFO mode and the I2C bus data repository under the LED display technology, assist in the preparation of the final bottom USB driver to achieve the firmware is automatically downloaded. After testing, the design of frame synchronization signal transmitter basic subjects required to achieve the basic principles of design and verification.
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Size: 603136 |
Author: xmuyfng |
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Description: sockt 5 代理服务器服务端程序，欢迎下载测试使用-In some graphics programs to run on a very low frame rate (FPS less than 10), which is due to create a D3D device caused by the vertical sync, I do not want to correct, and are interested in what can be changed. Repeat: this program needs to compile Visual C++2003, DirectX9.0, lua5.1 DirectX need to 2002/12/19 released DirectX9.0 version, you can download the following: http://www.microsoft.com/downloads/details.aspx? FamilyID = 124552ff-8363-47fd-8f3b-36c226e04c85 & DisplayLang = en
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Size: 32768 |
Author: dbcc |
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Description: 集中式插入式帧同步发的verilog源代码-concentrative inserted frame sync
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Size: 5120 |
Author: 白健 |
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Description: 这是一个帧同步数据搜索模块，用于检测输入的数据流中的帧头，当检测到帧头后输出一个同步信号。
输入数据为 8bit的并行数据流，数据流中的每帧由 10 个字节组成，为 1个字
节的帧头（47H）加上 9 个字节的数据。各个字节的中间部分与时钟上升沿对齐。
每帧数据中，除帧头外的其他数据也可能为 47H。
在数据传输过程中，帧头数据有可能受到干扰而变为其他数值，因此要求输出同步信号时具有一定的容错功能。-This is a frame synchronization data search module, for detecting the input data stream in the frame header, when the detected frame header and a synchronization signal after the output. 8bit parallel input data for the data flow, data flow in each frame consists of 10 bytes for a byte frame header (47H) plus 9 bytes of data. The middle part of each byte alignment with the clock rising edge. Each frame of data, in addition to other data outside the frame header may 47H. In the data transmission process, the frame header data may be subject to interference into other values, thus requiring the output sync signal has certain fault tolerance.
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Size: 409600 |
Author: 追月 |
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Description: 本程序实现了PCM30的帧同步和失步检测，采用verilog编程，包含了工程文件。-This procedure achieved PCM30 frame synchronization and detection step, using verilog programming, includes the project file.
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Size: 45056 |
Author: chenjian |
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Description: SDH帧同步头的检测，并提取其中的语音信息的模块设计-SDH frame sync detection, and extract audio information module design
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Size: 353280 |
Author: 雷伟林 |
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Description: 长帧同步时钟的产生功能模块，VHDL语言编写-Long frame sync clock generation function modules, VHDL language
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Size: 187392 |
Author: 王建伟 |
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Description: 1、搜索出数据流中的帧同步字信号，并给出帧同步标志。
2、系统工作开始后，要连续3次确认帧同步字进入锁定状态后才输出帧同步标志。
3、在锁定状态时，如连续出现3次错误的帧同步字，则帧同步标志输出无效，系统重新进入搜索状态；否则继续输出有效的帧同步标志。
-1, the search for the data stream signal in the frame synchronization word and frame synchronization flag is given. 2, the system works after the start of 3 consecutive times to confirm the frame synchronization word into the locked state after the output frame sync flag. 3, in the locked state, such as 3 consecutive incorrect frame synchronization word, the output frame sync flag is invalid, the system re-entering the search state otherwise continue to output a valid frame sync flag.
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Size: 5120 |
Author: your name |
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Description: 这是长帧同步时钟产生的Verilog源程序，已经编译通过，可以直接使用-This is a long frame sync clock generated Verilog source code, has been compiled by, can be used directly
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Size: 185344 |
Author: 莫然 |
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Description: 用verilog语言编写的帧同步搜索电路，输入数据data为8 bit并行数据流，基本结构为数据帧，帧长为10字节，帧同步字为H“FF”。clk为输入同步时钟。-Verilog language for frame synchronous search circuit, the input data is data for the 8-bit parallel data stream, the basic structure of the data frame, the frame length of 10 bytes, the frame synchronization word H "FF". clk to input sync clock.
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Size: 420864 |
Author: 眭明 |
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Description: sdh帧同步，实现sdh帧搜索，预同步，同步，保护等各态的功能-SDH frame synchronization SDH frame search, pre-sync, synchronization, protection, the function of each state
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Size: 59392 |
Author: 冷静思 |
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Description: HGE引擎修改。 1：dx8修改为dx9，帧率不做垂直同步，例子完整。 2：完美支持视频播放，创建视频纹理，可以随意使用。 3：添加雪花粒子系统类。 4：简单的视频滤镜，黑白、灰度。要修改代码才能看到，默认为无滤镜。 5：FLASH的支持，支持播放SWF。
注意：编译的可能会提示dxtrans.h文件找不到，解决办法注释掉该文件包含就可以！-HGE engine modifications. 1: dx8 modified dx9, not vertical sync frame, complete examples. 2: the perfect support for video playback, create video textures, free to use. 3: Add the snow particle system classes. 4: Simple video filters, black and white, grayscale. To modify the code to see that the default is no filter. 5: FLASH support, support for playback SWF. NOTE: You may be prompted dxtrans.h compiled file not found, the solution can be commented out the file contains!
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Size: 28286976 |
Author: chbha |
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Description: Virtual Frame: Sync Element Below Stack Pointer Source Code for Linux.
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Size: 3072 |
Author: jengzunvai |
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Description: orthogonal frequency division multiplexing frame sync original using square root
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Size: 2048 |
Author: karim moussa |
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