Search - FPGA NIOS

[Documents] nios_uart程序

Description: 该quartus的基于SOPC串口程序经过调试成功，对NIOS的初学者很有用。
Platform: | Size: 312320 | Author: angleboy | Hits:

[VHDL-FPGA-Verilog] std_cf_2c35

Description: 这个是基于NIOS II的FPGA平台的一个CF卡的接口模块，是在Quartus II下的完整工程包-NIOS II FPGA platform a CF card interface module, Quartus II is the complete package works
Platform: | Size: 399360 | Author: 佴立峰 | Hits:

[ARM-PowerPC-ColdFire-MIPS] para_serial

Description: FPGA内NIOSII核的并口，串口的初始化及其开发-NIOSII nuclear FPGA within the parallel port, serial port initialization and Development
Platform: | Size: 2048 | Author: liu | Hits:

[Embeded-SCM Develop] SIN_fashengqi

Description: 2006altera大赛－基于软核Nios的宽谱正弦信号发生器设计：摘要：本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台，将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上，利用直接数字频率合成技术、数字调制技术实现所要求波形的产生，用 FPGA 中的 ROM 储存 DDS 所需的波形表，充分利用片上资源，提高了系统的精确度、稳定性和抗干扰性能。使用新的数字信号处理（DSP）技术，通过在 Nios 中软件编程解决不同的调制方式的实现和选择。系统频率实现 1Hz～20MHz 可调，步进达到了1Hz；完成了调幅、调频、二进制 PSK、二进制 ASK、二进制 FSK 调制和扫频输出的功能。 -2006altera race-based soft-core Nios wide spectrum of sinusoidal signal generator design : Abstract : The use of design-based Nios II embedded processor SOPC technology. Altera Corporation system to the Cyclone FPGA series of digital platform, microprocessor, bus, Digital Frequency Synthesizer, memory and I/O interface hardware concentrated in an FPGA, the use of direct digital frequency synthesis technology and digital modulation waveforms required to achieve the rise, Using FPGA ROM storage of the DDS waveform table, and make full use of on-chip resources, improve the system's accuracy, stability and robustness. Use of new digital signal processing (DSP) technology, Nios through software programming to solve different ways of achieving modulation and choice. Realize the system freq
Platform: | Size: 407552 | Author: 刘斐 | Hits:

[VHDL-FPGA-Verilog] VGA_control_verilogHDL

Description: 基于FPGA的VGA控制器设计。对外支持普通VGA接口，以600×480的分辨率和60Hz扫描率为例。对内支持NIOSII软核接口。-FPGA-based VGA controller design. External support ordinary VGA interface, to 600 × 480 resolution and scan rate of 60Hz as an example. Internal support NIOSII soft-core interface.
Platform: | Size: 288768 | Author: Ray ZH | Hits:

[Embeded-SCM Develop] sd_ctl_nios

Description: 基于FPGA的SD控制器实现.目前实现读操作功能,可作参考.-FPGA-based SD controller. Nowadays Reading the functions, reference can be made.
Platform: | Size: 8192 | Author: zhou | Hits:

[Embeded-SCM Develop] USB_test

Description: NIOS II 与USB接口的程序，用于周立功FPGA的开发板，自己的开发板只需修改引脚即可-NIOS II with the USB interface procedures for weeks Ligong FPGA development board, its own development board can only modify pin
Platform: | Size: 60416 | Author: weikang | Hits:

[VHDL-FPGA-Verilog] eluosi_game

Description: 这是一个基于NIOSII的俄罗斯方块游戏设计，是基于FPGA的，利用流模式DMA传输实现游戏。-This is a box based on the Russian NIOSII game design, is based on the FPGA, and the use of streaming mode DMA transfer realize the game.
Platform: | Size: 8551424 | Author: 木易 | Hits:

[Embeded-SCM Develop] vgac_sst160aN

Description: 基于fpga和sopc的用VHDL语言编写的EDA的32位Nios CPU嵌入式系统及其DMA设计俄罗斯方块游戏机-FPGA and SOPC based on the use of VHDL language EDA 32-bit Nios CPU and the DMA design of embedded systems Tetris game
Platform: | Size: 2194432 | Author: 多幅撒 | Hits:

[ARM-PowerPC-ColdFire-MIPS] NIOS_new

Description: 基于Altera Cyclone系列FPGA的NIOS II开发板原理图，OrCAD格式-Based on the Altera Cyclone series FPGA-NIOS II development board schematic, OrCAD format
Platform: | Size: 617472 | Author: | Hits:

[Embeded-SCM Develop] FPGA_NIOS

Description: 高速FPGA（NIOS II）系统设计和实现-High-speed FPGA (NIOS II) system design and realization of
Platform: | Size: 96256 | Author: 11 | Hits:

[VHDL-FPGA-Verilog] Nios

Description: Altera公司开发的用于其FPGA的的Nios软核入门介绍-Developed by Altera for its FPGA of the Nios soft-core entry-Introduction
Platform: | Size: 1537024 | Author: liukun | Hits:

[Other] NIOS2full

Description: nios ii 完整版教程，学习fpga，实现32位处理器的嵌入式系统-nios ii full version of tutorial, learning fpga, realize 32-bit processors, embedded systems
Platform: | Size: 1745920 | Author: wuchangyu | Hits:

[VHDL-FPGA-Verilog] xd_lcd_comp

Description: 一款240＊128的LCD模块在ALTERA　FPGA　NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考-A 240* 128 LCD module in the ALTERA FPGA NIOS application, write your own AVALON Bus IP, including all source code can be easily used in NIOS for reference
Platform: | Size: 13312 | Author: 张敏 | Hits:

[Other] FPGANIOSkuaisurumenjiaocheng

Description: FPGA nios ii 快速入门教程适用于初学者简单易懂方便-FPGA nios ii QuickStart for easy convenience beginners
Platform: | Size: 2038784 | Author: 陈鹏 | Hits:

[Software Engineering] NiosII_implementation_in_CCD_Camera_for_Pi_of_the_

Description: The concept of the Altera Nios II embedded processor implementation inside Field Programmable Gate Array [FPGA] of the CCD camera for the “Pi of the Sky” experiment is presented. The digital board of the CCD camera, its most important components, current implementation of firmware [VHDL] inside the FPGA and the role of external 8051 microcontroller is briefly described. The main goal of the presented work is to get rid of the external microcontroller and to design new system with Nios II processor built inside FPGA chip. Constraints for implementing the design into the existing camera boards are discussed. New possibilities offered by a larger FPGA for next generation of cameras are considered.-The concept of the Altera Nios II embedded processor implementation inside Field Programmable Gate Array [FPGA] of the CCD camera for the “Pi of the Sky” experiment is presented. The digital board of the CCD camera, its most important components, current implementation of firmware [VHDL] inside the FPGA and the role of external 8051 microcontroller is briefly described. The main goal of the presented work is to get rid of the external microcontroller and to design new system with Nios II processor built inside FPGA chip. Constraints for implementing the design into the existing camera boards are discussed. New possibilities offered by a larger FPGA for next generation of cameras are considered.
Platform: | Size: 1427456 | Author: Francis Wu | Hits:

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