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[DSP program] lab0501-FIR

Description: TI DSP 5416 有限冲击FIR数字滤波器 设计例程-TI DSP 5416 a limited impact on the design of FIR digital filter routine
Platform: | Size: 11264 | Author: 陈洲 | Hits:

[Windows Develop] fir

Description: c语言实现的FIR滤波器，用户输入FIR滤波器的参数。-c language of the FIR filter, FIR filter user input parameters.
Platform: | Size: 206848 | Author: wangzhen | Hits:

[VHDL-FPGA-Verilog] fir

Description: code for fir filter see it is from altera site.-code for fir filter see it is from altera site.
Platform: | Size: 26624 | Author: bris | Hits:

[Embeded-SCM Develop] fir

Description: 使用verilog语言实现的fir滤波器，使用了内部的触发器资源，优化。-Verilog language used to achieve the fir filter, the use of internal resources of the flip-flop, and optimize.
Platform: | Size: 1024 | Author: liang jianbing | Hits:

[DSP program] FIR

Description: 在TMS320VC5509中，FIR滤波器的信号滤波-In TMS320VC5509 in, FIR filter signal filtering
Platform: | Size: 1024 | Author: 张苹 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 利用VHDL语言，设计了一个11阶的FIR滤波器。简单易懂-The use of VHDL language, designed a 11-order FIR filter. Easy to understand. .
Platform: | Size: 1024 | Author: 关小 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FIR of 1024 stage. 面向alteraFPGA器件设计-FIR of 1024 stage
Platform: | Size: 157696 | Author: 佴立峰 | Hits:

[Other] fir

Description: adsp bf533 实现 fir滤波的简单例程-bf533 achieve fir filtering routines
Platform: | Size: 78848 | Author: 徐海洋 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: fir filter design using vhdl codes
Platform: | Size: 1024 | Author: gowtham | Hits:

[VHDL-FPGA-Verilog] fir

Description: 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
Platform: | Size: 352256 | Author: hongwan | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。-FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.
Platform: | Size: 4096 | Author: 周州 | Hits:

[DSP program] FIR

Description: FIR低通滤波器，已在DSP试验箱上测试通过，希望对大家有帮助-FIR low-pass filter has been tested in the DSP chamber passed, want to help everyone
Platform: | Size: 1024 | Author: 小豆 | Hits:

[DSP program] fir

Description: fir dsp 的程序，经典的，不得不看-fir dsp programs, classic, and had to look at
Platform: | Size: 7168 | Author: xaoi | Hits:

[DSP program] fir

Description: 先用matlab得到所需滤波器的系数，将AD采样的数据经过fir滤波器后输出-First to use matlab to obtain the required filter coefficients, data from the AD sample, after the output filter through the fir
Platform: | Size: 2262016 | Author: 潘存华 | Hits:

[DSP program] FIR

Description: FIR滤波器在DSP TMS320C5402上的实现（C语言和汇编语言实现）-FIR filter in the DSP TMS320C5402 implementation (C and assembly language implementation)
Platform: | Size: 61440 | Author: 万文亮 | Hits:

[DSP program] FIR

Description: 用DSP来实现FIR滤波器。vectors.asm为汇编文件，main.c为主文件。-FIR filters with the DSP to achieve. vectors.asm for the compilation, main.c main document.
Platform: | Size: 450560 | Author: roar | Hits:

[DSP program] fir

Description: 窗口法设计fir低通滤波器matlab程序-Low-pass filter design fir
Platform: | Size: 1024 | Author: 张坤 | Hits:

[VHDL-FPGA-Verilog] fir-c2h

Description: 基于fpga的fir滤波器的设计 非常好，谢谢大家分享-fir filter design base on fpga it is very good
Platform: | Size: 11264 | Author: gary | Hits:

[DSP program] fir

Description: 基于SIMULINK中的DSPbuilder搭建的fir滤波器，可以任意修改阶数。系数需要自己填-Based on SIMULINK in DSPbuilder erected fir filters, you can arbitrarily modify the order of. Fill factor needs its own
Platform: | Size: 11264 | Author: 郑程 | Hits:

[Books] fir

Description: 本文以软件无线电为指导，提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构；然后采用模块化设计思想，将数字下变 频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计；最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
Platform: | Size: 201728 | Author: jiang | Hits:
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