Description: VHDL语言编写的fft变换的ip核代码 对算法感兴趣的可以-VHDL language fft transform algorithm ip core code can be interested in Platform: |
Size: 459776 |
Author:liujl |
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Description: cordic算法，包含所有的CORDIC的算法，与发表过的论文，与实现方案-CORDIC algorithm, contains all of the CORDIC algorithm, and published papers, and implementation of programs Platform: |
Size: 8102912 |
Author:elisen |
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Description: 附件代码实现了基4FFT的碟形单元运算，是FFT算法的核心部分，并且此碟形单元运算是基于浮点运算的-Annex code base of the dish 4FFT computing unit is the core of the FFT algorithm, and this dish is based on the computing unit of the floating-point operations Platform: |
Size: 4096 |
Author:钟毓秀 |
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Description: :文章针对目前数字信号处理中大量采用的快速傅立叶变换[FFT] 算法采用软件编程来处理的应用现状,在对FFT 算法进行
分析的基础上,给出了用FPGA[Field Programmable Gate Array] 实现的8 点32 位FFT 处理器方案,并得到了系统的仿真结果。
最后在Altera 公司FLEX10K系列FPGA 芯片上成功地实现了综合。-Based on the analysis of the FFT algorithm , a reasonable logic structure for a 8-point ,32- bit FFT processor is described and the simulating
result is given in this paper. The processor is implemented on the FLEX10Kfamily of FPGAs. Platform: |
Size: 220160 |
Author:王晓 |
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Description: 针对高速数字信号处理的要求,提出用FPGA 实现基- 4FFT 算法,并对其整体结构、蝶形单
元进行了分析. 采用蝶算单元输入并行结构和同址运算,能同时提供蝶形运算所需的4 个操作
数,具有最大的数据并行性,能提高处理速度 按照旋转因子存放规则,蝶形运算所需的3 个旋转
因子地址相同,且寻址方式简单 输出采取与输入相似的存储器 运算单元同时采用3 个乘法的
复数运算算法来实现.-In accordance with the requirements of high speed digital signal processing , the algorithmof radix
O4 implemented with FPGA and the integrated architecture and butterfly unit are analyzed. With butterfly u2
nit input which is designed by parallel structure and the same address calculation , four operation codes the
butterfly unit needs can be provided simultaneously to have the most data parallel and improve the speed of
calculation. According to the rotation parameters memory regulation , the addresses of three rotation parame2
ters of butterfly unit are the same with simple style of address generation and similar input and output memo2
ries. The operating unit adopted is implemented by three complex calculation algorithm of multiplication si2
multaneously. Platform: |
Size: 360448 |
Author:王晓 |
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Description: 基于FPGA的FFT的硬件实现。其中含有部分vhdl程序，本论文采用基4FFT算法-FPGA-based hardware implementation of the FFT. Vhdl part which contains the procedures used in this paper-based algorithm 4FFT Platform: |
Size: 942080 |
Author:xyyj |
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Description: 基于VHDL语言的一个FFT快速傅里叶变换程序。采用4蝶形算法-VHDL language based on a FFT Fast Fourier Transform procedure. 4 butterfly algorithm used Platform: |
Size: 180224 |
Author:李超 |
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Description: 计算离散傅里叶变换的一种快速算法,简称FFT。快速傅里叶变换是1965年由J.W.库利和T.W.图基提出的。采用这种算法能使计算机计算离散傅里叶变换所需要的乘法次数大为减少,特别是被变换的抽样点数N越多,FFT算法计算量的节省就越显著。
-Discrete Fourier transform calculation of a fast algorithm, referred to as FFT. Fast Fourier Transform in 1965 by JW Cooley and TW map out Kormakiti. This algorithm enables calculation of discrete Fourier transform computer required a significant reduction in the number of multiplication, in particular by changing the sampling points N more, FFT algorithm for calculating the amount of savings will be significant. Platform: |
Size: 1024 |
Author:圈石 |
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Description: 给出了16位浮点FFT的算法代码及相关资料-Given a 16-bit floating-point FFT algorithm code and related information Platform: |
Size: 418816 |
Author:陈少飞 |
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Description: CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and
a configurable number of sample points in the FFT.
Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the
CFFT core to be different from the standard FFT algorithm. This variation in gain
is not important for orthogonal frequency division modulation (OFDM) and demodulation.
The gain can be corrected, to that of a conventional FFT, by applying a constant
multiplying factor.
Platform: |
Size: 183296 |
Author:Nagendran |
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Description: 本文给出一种基于FPGA的新型谐波检测系统的设计方案。在该方案中，采用FPGA实现快速的FFT运算，采用数字锁相环来同步被测信号，以减小由非同步采样所产生的误差并给出实现的设计实现。数字锁相环和FFT算法用VHDL语言设计实现，该方案能提高谐波分析的精度以及响应速度,同时大大地精简了硬件电路, 系统升级非常方便。-This paper presents a new FPGA-based harmonic detection system design. In the scheme, using the FFT for fast FPGA computing, digital phase-locked loop to synchronize the measured signal to reduce the non-synchronous sampling error arising from implementation of the design and implementation are given. Digital PLL and FFT algorithm design and implementation using VHDL language, the program can improve the accuracy of harmonic analysis and response speed, and greatly streamline the hardware circuit, the system is very easy to upgrade. Platform: |
Size: 18432 |
Author:何正亚 |
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Description: Implementing the Radix-4 Decimation
in Frequency (DIF) Fast Fourier
Transform (FFT) Algorithm Using a
TMS320C80 DSP Platform: |
Size: 150528 |
Author:seojinwon |
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Description: The Fast Fourier Transform (FFT) is one of the
rudimentary operations in field of digital signal and image
processing. Some of the very vital applications of the fast
fourier transform include Signal analysis, Sound filtering, Data
compression, Partial differential equations, Multiplication of
large integers, Image filtering etc.Fast Fourier transform
(FFT) is an efficient implementation of the discrete Fourier
transform (DFT). This paper concentrates on the development
of the Fast Fourier Transform (FFT), based on Decimation-In-
Time (DIT) domain, Radix-2 algorithm, this paper uses VHDL
as a design entity, and their Synthesis by Xilinx Synthesis Tool
on Vertex kit has been done. The input of Fast Fourier
transform has been given by a PS2 KEYBOARD using a
testbench and output has been displayed using the waveforms
on the Xilinx Design Suite 12.1.The synthesis results show that
the computation for calculating the 32-point Fast Fourier
transform is efficient in terms of speed. Platform: |
Size: 305152 |
Author:doggaravi |
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Search - FFT algorithm in vhdl