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[Other resource] div3 DL : 0: VHDL实现50％占空比。并且是奇数分频。
Date : 2008-10-13 Size : 115.48kb User : skylinnan
[Other resource] div3 DL : 0: 用VHDL硬件描述语言实现的良好运行的三分频电路
Date : 2008-10-13 Size : 1.03kb User : 赵杰
[VHDL-FPGA-Verilog] div3 DL : 0: VHDL实现50％占空比。并且是奇数分频。-VHDL to achieve 50 duty cycle. And is odd-numbered sub-frequency.
Date : 2025-07-09 Size : 115kb User : skylinnan
[VHDL-FPGA-Verilog] div3 DL : 0: 用VHDL硬件描述语言实现的良好运行的三分频电路-Using VHDL hardware description language to achieve a good run of one-third frequency circuit
Date : 2025-07-09 Size : 1kb User : 赵杰
[ELanguage] div3 DL : 0: flex code，compiler theory curriculum design, the C write PL / 0 compiler, a detailed documentation and code -flex code, compiler theory curriculum design, the C write PL/0 compiler, a detailed documentation and code
Date : 2025-07-09 Size : 39kb User : yn
[VHDL-FPGA-Verilog] Div3 DL : 0: 一个除3器的Verilog源码，用于视频解码器的熵解码部分。纯组合逻辑，大小和加法器差不多。-In addition to device a Verilog source code 3, the video decoder for entropy decoding part. Pure combinational logic, about the size and adder.
Date : 2025-07-09 Size : 104kb User : 闫煜
[VHDL-FPGA-Verilog] div3 DL : 0: 实现三分频功能，占空比为50 ，可以很好的用于解决课程设计问题！-This is used for divide the frequency,and the duty cycle is 50 .
Date : 2025-07-09 Size : 255kb User :