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[Other resource] SEG7_LUT_8

Description: DE2板子附带的7段数码管 IPCORE 有兴趣的朋友可以下载
Platform: | Size: 12299 | Author: huang | Hits:

[Other resource] shuzixitongshiyan

Description: 这个给QuartusII初学者用的，里面很清楚的通过几个例子来告诉怎么运用QuartusII．实验1：Quartus入门实验2：简单的组合逻辑电路设计实验3：七段数码管显示实验4：BCD码显示及运实验5：触发器和计数器实验6：存储器的设计实验7：基于DE2 的SOPC系统开发附录：
Platform: | Size: 755392 | Author: yulieyar | Hits:

[Other resource] test

Description: 使用VHDL语言，对Altera公司的DE2开发板进行开发，本例实现了对板上7段数码管的显示，在niosiiIDE上基于硬件实现小灯的循环亮灭
Platform: | Size: 55474 | Author: 张好 | Hits:

[Embeded-SCM Develop] DE2_Default

Description: his design is the initial design when the board is powered-up. It increments a counter and displays the value on the 7-segment displays and LEDs. An image is also displayed on the VGA port.-his design is the initial design when the bo ard is powered-up. It increments a counter and d isplays the value on the 7-segment displays and LEDs. An image is also displayed on the VGA port.
Platform: | Size: 270336 | Author: 木易 | Hits:

[Other Embeded program] SEG7_LUT_8

Description: DE2板子附带的7段数码管 IPCORE 有兴趣的朋友可以下载-DE2 board attached to 7 digital tube IPCore friends are interested in can be downloaded
Platform: | Size: 12288 | Author: huang | Hits:

[VHDL-FPGA-Verilog] shuzixitongshiyan

Description: 这个给QuartusII初学者用的，里面很清楚的通过几个例子来告诉怎么运用QuartusII．实验1：Quartus入门实验2：简单的组合逻辑电路设计实验3：七段数码管显示实验4：BCD码显示及运实验5：触发器和计数器实验6：存储器的设计实验7：基于DE2 的SOPC系统开发附录：-This QuartusII beginners to use, which is very clear through several examples to tell how the use of QuartusII. Experiment 1: Quartus entry Experiment 2: a simple combinational logic circuit design of experiment 3: Seven-Segment LED display experiment 4: BCD code display and shipped experiment 5: flip-flops and counters experiment 6: the design of memory test 7: Based on DE2 the SOPC System Development Appendix:
Platform: | Size: 754688 | Author: yulieyar | Hits:

[VHDL-FPGA-Verilog] avalon_chk_vhd

Description: de2 avalon checksum by vhdl -de2 avalon checksum by vhdl
Platform: | Size: 23552 | Author: You | Hits:

[VHDL-FPGA-Verilog] test

Description: 使用VHDL语言，对Altera公司的DE2开发板进行开发，本例实现了对板上7段数码管的显示，在niosiiIDE上基于硬件实现小灯的循环亮灭-Using VHDL language, on Altera s DE2 development board for development, which in this case the realization of paragraph 7 of the on-board digital tube display, in niosiiIDE hardware implementation based on a small circle of bright lights out
Platform: | Size: 55296 | Author: 张好 | Hits:

[SCM] 16bit_display8bitLED

Description: Abstract七段显示器在DE2可当成Verilog的console，做为16进位的输出结果。Introduction使用环境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)简单的使用switch当成2进位输入，并用8位数的七段显示器显示16进位的结果。-Abstract Seven-Segment Display as Verilog to DE2 at the console, as 16 of the output binary. Introduction to use the environment: Quartus II 7.2 SP1+ DE2 (Cyclone II EP2C35F627C6) the use of a simple switch as a binary input 2, and paragraph 8-digit binary display 16 results.
Platform: | Size: 7168 | Author: 王媛媛 | Hits:

[VHDL-FPGA-Verilog] SEG7_LUT_8_0

Description: DE2开发平台7段显示VHDL代码，自己针对vilorg翻译成VHDL代码-DE2 Development Platform 7 show the VHDL code for vilorg translated into their own VHDL code
Platform: | Size: 1024 | Author: siubr | Hits:

[VHDL-FPGA-Verilog] DE2

Description: 使用 DE2板制作的多功能数字钟，含有选择功能，秒表，电子表，闹钟，用7-segment LED液晶显示，可以通过LCD看当时状态附有仿真波形--Clk_Div,- Mode_Select,-Watch,-stop_watch,-Lcd_Module,-Total_Out source code，Simulation waveform
Platform: | Size: 3694592 | Author: 赵香君 | Hits:

[Other] DE2_SOPC_hardware_development

Description: 本书对国内高校中广泛使用的Altera DE2 SOPC开发平台的硬件设计进行了较为详细的分析，介绍了FPGA与SOPC的设计流程，并通过大量的练习详细地介绍了如何在DE2平台上进行从简单到复杂的数字系统设计。全书分为7章，包括FPGA基本概念与DE2开发平台、FPGA设计流程、SOPC技术、DE2平台应用、基于Altera FPGA的DSP技术、数字系统设计练习及“计算机组成原理”课程练习。本书配有光盘一张，包含了DE2系统的内容及DE2的高级应用范例。本书可作为电子类、计算机类、自动化类、机电类等专业本科生和研究生的教材或教学参考书，也可作为数字电子电路设计人员和大规模集成电路设计工程师的参考书。-This book on the domestic colleges and universities are widely used in Altera DE2 SOPC hardware development platform for the design of a more detailed analysis, introduced the FPGA and SOPC design flow, and through a lot of practice in detail how to DE2 platform from simple to the design of complex digital systems. The topics are divided into 7 chapters, including the basic concepts of FPGA with the DE2 development platform, FPGA design flow, SOPC technology, DE2 platform, the Altera FPGA-based DSP technology, digital system design practice and the "Principles of Computer Organization" course to practice. Book with a CD-ROM contains the contents of the DE2 System and DE2 examples of advanced applications. This book can be used as electronic, computer, automation categories, such as Electrical and professional undergraduate and postgraduate teaching materials or teaching reference books can also be used as the design of digital electronic circuits and large-scale integrated circuits
Platform: | Size: 33057792 | Author: 邱浩淼 | Hits:

[VHDL-FPGA-Verilog] HEX_DISPLAY

Description: Simple vhdl description to show numbers on 7-segment s on Altera DE2 board.
Platform: | Size: 310272 | Author: kvasir | Hits:

[VHDL-FPGA-Verilog] LEDtest

Description: 简单的7段数码管驱动，对应de2，可直接用，内含de2板子的管脚分配-Simple digital control driver 7, corresponding to de2, can be directly used, containing de2 board pin allocation
Platform: | Size: 608256 | Author: 袁野 | Hits:

[VHDL-FPGA-Verilog] DE2shijian(7)

Description: FPGA与SOPC设计教程：DE2实践-第七章计算机组成原理练习-FPGA and SOPC design tutorials: DE2 Practice- Practice Computer Organization Chapter VII
Platform: | Size: 4526080 | Author: lutangshi | Hits:

[VHDL-FPGA-Verilog] part2

Description: Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX2− 0. Derive a control signal, from the 50-MHz clock signal provided on the DE2 board, to increment the contents of the counter at one-second intervals. Use the pushbutton switch KEY0 to reset the counter to 0.
Platform: | Size: 552960 | Author: echo | Hits:

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