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[Software EngineeringeeDDS

Description: EDA实验本科论文,对学习电子工程专业的学生有很大帮助,是关于直接数字频率合成器的-EDA experimental undergraduate thesis on the study of electronic engineering students to be of great help. of direct digital frequency synthesis of
Platform: | Size: 604160 | Author: 王琨 | Hits:

[matlabperiodogramestimate

Description: Generate 100 samples of a zero-mean white noise sequence with variance , by using a uniform random number generator. a Compute the autocorrelation of for . b Compute the periodogram estimate and plot it. c Generate 10 different realizations of , and compute the corresponding sample autocorrelation sequences , and . Compute the average autocorrelation sequence as and the corresponding periodogram for . d Compute and plot the average periodogram using the Bartlett method. e Comment on the results in parts (a) through (d). -Generate 100 samples of a zero-mean white noise sequence with variance, by using a uniform random number generator.a Compute the autocorrelation of for. B Compute the periodogram estimate and plot it. C Generate 10 different realizations of, and compute the corresponding sample autocorrelation sequences, and. Compute the average autocorrelation sequence as and the corresponding periodogram for. d Compute and plot the average periodogram using the Bartlett method. e Comment on the results in parts (a) through (d).
Platform: | Size: 1024 | Author: 冀晗 | Hits:

[WaveletDDS

Description: 利用EDA技术和FPGA在UP3开发板上实现直接数字频率综合器的设计。 实验中加入了相位控制字PWORD,用以控制相位偏移量的前四位,将相位偏移量加到ROM地址总线 上,从而引起从ROM中取得的正弦信号的偏移,实现移相信号发生器的移相功能。 实验中还加入了LCD显示功能,通过LCD显示模块器件,用LCD显示正弦信号的频率,所显示的频 率也是由频率字控制的。LCD的驱动原理同上次实验。-The use of EDA technology and FPGA development in the UP3 board direct digital frequency synthesizer design. Experiment by adding a phase control word PWORD, to control the phase offset of the top four will be added to the phase offset ROM address bus, thereby causing ROM obtained from the sinusoidal signal offset, shifted believe realize its phase-shifting function generator. Experiments have also joined the LCD display, LCD display module through the device, with LCD display the frequency of sinusoidal signal, as shown by the frequency of word frequency control. LCD driving principles with the previous experiment.
Platform: | Size: 1225728 | Author: Emma | Hits:

[OtherAD9850Design

Description: dds开发工具,可验证你的频率算法是否正确,-dds development tools, verifiable frequency of your algorithm is correct,
Platform: | Size: 123904 | Author: liuli | Hits:

[VHDL-FPGA-VerilogDDS

Description: 基于EPM7128的数字合成信号发生器(DDS)设计。通过对EPM7128编程,组合出地址累加器、数据锁存器、256*8位ROM空间。外接DA可实现正弦波输出功能-EPM7128-based signal generator for digital synthesis (DDS) design. EPM7128 through programming, the combination of address accumulator, data latches, 256* 8 ROM space. DA external sine wave output function can be realized
Platform: | Size: 354304 | Author: xiaoyu | Hits:

[Communicationdds_matlab

Description: 利用Matlab软件编程实现DDS(直接数字频率合成技术)。设时钟的频率为固定值f_C,在CLK的作用下,如果按照0000,0001,0010,…,1111的地址顺序读出ROM中的数据,即表1中的幅值编码,其正弦信号频率为f_01;如果每隔一个地址读一次数据(即按0000,0001,0100,…,1110顺序),其输出信号频率为f_02,且f_02将比f_01提高一倍,即f_02=2f_01;其余类推。这样,就可以实现直接数字频率合成器的输出频率的调节。-Matlab software programming DDS (direct digital frequency synthesis). Clock frequency set to a fixed value f_C, under the effect of CLK, according to 0000,, ..., 1111 of the sequence of addresses in the ROM reads the data, i.e., the amplitude of the encoding in Table 1, the frequency of the sinusoidal signal f_01 if every time a read address data (ie 0000,0001,0100, ..., the order of 1110), the output signal frequency is f_02, and f_02 f_01 than doubled, i.e. f_02 = 2f_01 rest on. This allows direct digital frequency synthesizer output frequency regulation.
Platform: | Size: 13312 | Author: tom ke | Hits:

[matlabread_SRTMtile

Description: 读取高程数据的MATLAB程序,经过测试,很不错的,希望对大家有帮助- read_SRTMtile: returns lon, lat, & height (height in meters) SRTM 3-arcsec data USE: [vlon vlat vhgt] read_SRTMtile(filename,sc) INPUT: filename: filename, e.g. s23w041.hgt sc: spot check, any value here will produce a low resolution image of tile (note: image rendering can be time consuming) OUTPUT: vlon: cell longitude vlat: cell latitude vhgt: cell height (in meters) NOTES: + SRTM 3-arc sec data can be downloaded from: http://dds.cr.usgs.gov/srtm/version2_1/SRTM3/ (as per http://www2.jpl.nasa.gov/srtm/) + filename is parsed to obtain lower left (LL) coordinates of tile (as per quickstart.pdf doc in: http://dds.cr.usgs.gov/srtm/version2_1/Documentation/ File names refer to the latitude and longitude of the lower
Platform: | Size: 2048 | Author: zzg | Hits:

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