Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - DDR controller lattice

Search list

[Other resource] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 678583 | Author: 钟方 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 677888 | Author: 钟方 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA-DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
Platform: | Size: 676864 | Author: 黄达 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM_controller

Description: ddr sdram控制器，lattice器件的参考设计，比较详细-ddr sdram controller, lattice components of the reference design, very detailed
Platform: | Size: 693248 | Author: | Hits:

[VHDL-FPGA-Verilog] DDRsdram2

Description: 一个DDR2 的控制器源码，它是由LATTICE的编译器生成。-A DDR2 controller source code, which is generated by the compiler LATTICE.
Platform: | Size: 969728 | Author: 召唤 | Hits:

[VHDL-FPGA-Verilog] lattice_ddr_verilog-for-orca4

Description: 莱迪思的DDR控制器源码（包括仿真与说明文档），DDR为MT46V16M8，Verilog-The DDR controller source of Lattice (including simulation and documentation), DDR is MT46V16M8, Verilog
Platform: | Size: 615424 | Author: 刘佳庆 | Hits:

CodeBus www.codebus.net