Location:
Search - DDR TIMING
Search list
Description: 关于DDR SDRAM的详细原理和时序分析,对于开发设计有很大使用价值-DDR SDRAM on detailed principles and timing analysis, design for the development of a great value
Platform: |
Size: 2201600 |
Author: 王平 |
Hits:
Description: DDR2时序规范，DDR·
DDR2时序规范，DDR·-DDR2 timing norms, DDR DDR2 timing norms, DDR
Platform: |
Size: 1933312 |
Author: yangjian |
Hits:
Description: i2cinterface.v是我自己写的一段verilog代码，在接口为I2C接口的芯片设计中用到。送去流过片，仅作参考用。
debussy和modelsim协同仿真.txt 用于debussy和modelsim协同仿真时参考
RTL Coding and Optimization Guide for use with Design Compiler.pdf
数提讲座（1）.wmv
数提讲座（2）.wmv这两个视频和一篇文档对数字IC前端设计师的设计提高很有帮助，如果你觉得你到瓶颈状态了，想提高的话，强烈建议好好看看。
ADVANCED ASIC CHIP SYNTHESIS中文翻译资料.ppt这也是我极力推荐的，相信学习dc的人都知道原英文文档。这个ppt相当于翻译版，对dc和pt中文详细阐述。
基于DDR SDRAM控制时序分析的模型.pdf
全定制单元时序模型的建立.pdf 这两篇文档是用作建议时序模型的时候用作参考，是我花了小money买的哦。
数字IC设计全程实例.pdf 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从设计的系统行为级描述或RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真.
-i2cinterface.v a section of my own writing verilog code for the I2C interface in the interface used in chip design. Sent to flow through the film, only for reference.
debussy and modelsim co-simulation. txt for debussy and modelsim co-simulation reference
RTL Coding and Optimization Guide for use with Design Compiler.pdf
Mention the number of lectures (1). Wmv
Mention the number of lectures (2). Wmv the two videos, and the document is useful for the digital front-end IC designers to improve the design capability. if you think you go to bottleneck, and want to improve, then it is strongly recommended a good look.
ADVANCED ASIC CHIP SYNTHESIS Chinese translation of the information. Ppt that is what I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese .
DDR SDRAM control the timing analysis based on the model. Pdf
Platform: |
Size: 20989952 |
Author: 喻琪 |
Hits:
Description: 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400
(PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes the Virtex ™ -5 devices to achieve 200 MHz DDR SDRAM (JEDEC DDR400
(PC3200) standard) controller. The Design and Implementation of the use of IDELAY unit to adjust read data timing. Reading the data calibration and adjust the timing for completion of this controller.
Platform: |
Size: 408576 |
Author: 陈阳 |
Hits:
Description: xilinx公司原版的DDR时序控制源码.-xilinx' s original source code of the DDR timing control.
Platform: |
Size: 680960 |
Author: suyufeng |
Hits:
Description: 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is OSCI SystemC 2.2.0. All of the hardware modules satisfies the OSCI standards.
The simulator is composed of a CPU, cache, and memory components including DDR SDRAM, MLC NOR Flash, MLC NAND Flash, SRAM. Each memory components have it’s own memory model, which enables cycle-accurate power consumption estimation of the devices. Master and slave SystemC IPs are connected through AMBA AHB CLI (Cycle-Level Interface). You will get energy trace files for each memory devices. You will get cycle-accurate performance evaluation results CPU cycle counts information, and cache hit/miss ratio on console. Also, you can get trace files for memory devices.
The simulator exhibits performance over 500 K instructions/sec, which is fairly high for a cycle-accurate system-level simulator.
The simulator’s source co
Platform: |
Size: 4886528 |
Author: Archie |
Hits:
Description: 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
Platform: |
Size: 2525184 |
Author: 张桃源 |
Hits:
Description: DDR SDRAM总结文档，描述了DDR IP的设计挑战，接口时序，模块设计原则，调试技巧及应用指南-DDR SDRAM summary document describing the design challenge of DDR IP, interface timing, modular design principles, debugging skills and Application Guide
Platform: |
Size: 338944 |
Author: 李中梅 |
Hits:
Description: 内存的原理和时序(SDRAM、DDR、DDR-Ⅱ、Rambus_DRAM)-The principle and the timing of the memory (SDRAM, DDR, DDR-II, Rambus_DRAM)
Platform: |
Size: 7368704 |
Author: 李先生 |
Hits:
Description: DDR addressing details and AC timing parameters from JEDEC specs.
Platform: |
Size: 1024 |
Author: qeilagui |
Hits:
Description: 一个关于音频播放的fpga驱动代码。流程是从sd卡中读取音频文件，然后缓存到DDR中，再通过一定的时序关系让音频WM8731芯片播放-An audio playback on fpga driver code. The process is to read audio files from sd card and then cached to DDR, and then through a certain timing relationships allow playback of audio WM8731 chip
Platform: |
Size: 215040 |
Author: lilianghua |
Hits:
Description: DDR addressing details and AC timing parameters JEDEC specs.
-DDR addressing details and AC timing parameters JEDEC specs.
Platform: |
Size: 1024 |
Author: kycongong |
Hits:
Description: describe synopsis ommonly use double data rate (DDR) memory IP to boost memory bandwidth, but they
often struggle to meet timing budgets for these high-speed interfaces. Designers who incorporate DDR
IP into systems-on-chip (SoCs) and use external DRAM have little control over the timing c
Platform: |
Size: 580608 |
Author: hasan |
Hits:
Description: 嵌入式DDR时序方面的书籍，对调试时序有帮助(The principle and timing.Rar of DDR)
Platform: |
Size: 2200576 |
Author: andy_zeng6
|
Hits: