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[Compress-Decompress algrithms] jpeg_encoder

Description: 完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路-complete jpeg encoder Verilog code, DCT is partly based on the IEEE 1991 transection paper, using skew circular convolutions to achieve streamlining circuit
Platform: | Size: 25437 | Author: 李寧 | Hits:

[Special Effects] DCTofJPEG

Description: 用verilog代码写的JPEG压缩核心模块DCT变换之蝶形单元算法-verilog code written using JPEG compression core module DCT's butterfly modules algorithm
Platform: | Size: 1645 | Author: 叶人杰 | Hits:

[Compress-Decompress algrithms] jpeg_encoder

Description: 完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路-complete jpeg encoder Verilog code, DCT is partly based on the IEEE 1991 transection paper, using skew circular convolutions to achieve streamlining circuit
Platform: | Size: 25600 | Author: 李寧 | Hits:

[Compress-Decompress algrithms] 601792346200732319490634862

Description: jpeg压缩中的DCT蝶型算法verilog代码-jpeg DCT compression algorithm verilog code BUTTERFLY
Platform: | Size: 5120 | Author: wuguanying | Hits:

[Special Effects] DCTofJPEG

Description: 用verilog代码写的JPEG压缩核心模块DCT变换之蝶形单元算法-verilog code written using JPEG compression core module DCT's butterfly modules algorithm
Platform: | Size: 1024 | Author: 叶人杰 | Hits:

[Graph program] DCT-vhdl

Description: 这是一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT)算法,采用VHDL实现-This is a two-dimensional 8* 8 discrete cosine transform (DCT) and inverse transform (IDCT) algorithms using VHDL realize
Platform: | Size: 10240 | Author: liujl | Hits:

[VHDL-FPGA-Verilog] DCT

Description: 用verilog语言实现DCT编解码 附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
Platform: | Size: 65536 | Author: 周韧研 | Hits:

[Multimedia program] dct

Description: Mpeg2视频压缩时进行空间压缩时的离散余弦变换矩阵的verilog实现，采用modelsim验证-Mpeg2 video compression when space compression of discrete cosine transform matrix realize Verilog using ModelSim verification
Platform: | Size: 29696 | Author: mayang | Hits:

[source in ebook] 63535312DCTofJPEG

Description: 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
Platform: | Size: 2048 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] OneD_DCT8

Description: 一维DCT变换，使用Verilog ＨＤＬ语言实现。有ＳＹｎｐｌｉｆｙ编译脚本-One-dimensional DCT, using the Verilog HDL language to achieve. The SYnplify compiled script
Platform: | Size: 2048 | Author: 海峰 | Hits:

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