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[Embeded-SCM Develop] pci

Description: altera pci license al tera pci license -altera pci license al tera pci license
Platform: | Size: 1024 | Author: wang | Hits:

[Other] PCI_User_Manual

Description: The Cyclone® III PCI development board provides a hardware platform for developing and prototyping low-power, high-performance, logic-intensive PCI-based designs. The board provides a high-density of the memory to facilitate the design and development of FPGA designs which need huge memory storage, and also includes Low-Voltage Differential Signaling (LVDS) interface of the High-Speed Terasic Connectors (HSTCs) for extra high-speed interface application.-The Cyclone ? III PCI development board provides a hardware platform for developing andprototyping low-power, high-performance, logic-intensive PCI-based designs. The board provides ahigh-density of the memory to facilitate the design and development of FPGA designs which needhuge memory storage, and also includes Low-Voltage Differential Signaling (LVDS) interface ofthe High-Speed Terasic Connectors (HSTCs) for extra high-speed interface application.
Platform: | Size: 2132992 | Author: 张治国 | Hits:

[VHDL-FPGA-Verilog] sopcfpga

Description: 一个Altera Cyclone PCI开发板的配套样板源代码-Sample source code for An Altera Cyclone PCI development board
Platform: | Size: 4057088 | Author: Joe | Hits:

[Software Engineering] EP2C35_PCI

Description: 文章描述了FPGA的CYCLONE II系列芯片的PCI的最小系统的相关参考资料，对于初学者有很大的帮助！-Article describes the CYCLONE II family of FPGA-chip PCI-minimum system-related references, very helpful for beginners!
Platform: | Size: 408576 | Author: 张成 | Hits:

[VHDL-FPGA-Verilog] testbench

Description: altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。-altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.
Platform: | Size: 1759232 | Author: greenpine | Hits:

[VHDL-FPGA-Verilog] pci32tlite_oc_latest.tar

Description: pci32 taget core ip, The core has been designed to permit interface between a PCI Master and simple WHISBONE Slaves, and fitting into smallest FPGA (about 200 LC s in ALTERA CYCLONE II FPGA).-pci32 taget core ip, The core has been designed to permit interface between a PCI Master and simple WHISBONE Slaves, and fitting into smallest FPGA (about 200 LC' s in ALTERA CYCLONE II FPGA).
Platform: | Size: 7813120 | Author: shen | Hits:

[VHDL-FPGA-Verilog] PCIe_Lab(ALTERA-V5PCIe)

Description: 这一设计实例深入浅出，介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。 -Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.
Platform: | Size: 6629376 | Author: 微笑 | Hits:

[Software Engineering] EasyGX_V1.0_SCH

Description: EasyGX Cyclone® IV GX电路原理图，包括基于FPGA的PCI Express和10/100/1000M以太网接口相关电路。-The EasyGX Cyclone® IV GX development kit is especially suitable for develop and test PCI Express and 10/100/1000M Ethernet interface, including NIOS II embedded CPU and USB-Blaster function, which provided rich external memory for rapid prototype environment.
Platform: | Size: 220160 | Author: 王广龙 | Hits:

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