Description: 一本关于复位说明的很好的文章。上面详细的介绍了同步复位和异步复位的区别。和应用。对于电路设计的人很有用-a note on the reduction of a good paper. Above a detailed introduction to the synchronous and asynchronous reset reduction distinction. And application. Circuit design for the very useful Platform: |
Size: 243056 |
Author:yinlq |
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Description: 基于VHDL的串行异步通信电路的设计
包括串行发送器，异步接收器，以及控制器
vhdl-VHDL-based serial asynchronous communication circuit design, including serial transmitter, asynchronous receiver. and controller vhdl Platform: |
Size: 4352 |
Author:那锋 |
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Description: 一本关于复位说明的很好的文章。上面详细的介绍了同步复位和异步复位的区别。和应用。对于电路设计的人很有用-a note on the reduction of a good paper. Above a detailed introduction to the synchronous and asynchronous reset reduction distinction. And application. Circuit design for the very useful Platform: |
Size: 242688 |
Author:yinlq |
Hits:
Description: 基于VHDL的串行异步通信电路的设计
包括串行发送器，异步接收器，以及控制器
vhdl-VHDL-based serial asynchronous communication circuit design, including serial transmitter, asynchronous receiver. and controller vhdl Platform: |
Size: 4096 |
Author:飘来的南风 |
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Description: willey出版的异步电路设计英文版，详细介绍了异步电路设计方法，相信对做硬件的有帮助-Willey asynchronous circuit design published in English, detailed information on asynchronous circuit design method, believed to be helpful to make hardware Platform: |
Size: 32311296 |
Author:惠飞 |
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Description: This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 µ m CMOS process and it shows a power advantage of a factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the synchronous implementation, and timing compatible for external memory access. The circuit is a compiled VLSI-program, using Tangram as VLSI-programming language and the Tangram tool set to compile the design automatically to a standard-cell netlist. This design approach proves to be powerful enough to describe the microcontroller and derive an efficient implementation. Further, it offers the designer the possibility to explore various alternatives in the design space. Platform: |
Size: 98304 |
Author:啊灿 |
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Description: 基于VHDL的异步串行通信电路设计 随着电子技术的发展，现场可编程门阵列FPGA和复杂可编程逻辑器件CPLD的出现，使得电子系统的设计者利用与器件相应的电子CAD软件，在实验室里就可以设计自己的专用集成电路ASIC器件。这种可编程ASIC不仅使设计的产品-VHDL-based asynchronous serial communication circuit design with the advent of electronic technology, field programmable gate array FPGA and CPLD Complex Programmable Logic Device emergence, the designers of electronic systems and devices using the corresponding electronic CAD software , in the laboratory can design their own application-specific integrated circuits ASIC devices. This not only makes the design of Programmable ASIC products Platform: |
Size: 1024 |
Author:chaiyiming |
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Description: 详细介绍PIC单片机使用SPI方式与IC卡进行数据传输的原理和电路设计，以及使用USART方式与PC机进行串行异步通信的工作原理；介绍PIC单片机听SPI方式和USART方式的设置方法。-PIC detailed the use of SPI with Single-chip IC card for data transmission principles and circuit design, as well as with the PC using USART serial asynchronous communication for conducting the working principle to listen to introduce single-chip microcomputer PIC mode and SPI mode USART Ways settings. Platform: |
Size: 215040 |
Author:蚊子 |
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Description: 分别完成了异步发送电路，接收电路的设计，并把发送和接收电路组合在一起，构成通信控制器。-Send completed asynchronous circuit, receiving circuit design, and to send and receive circuit together constitute the communication controller. Platform: |
Size: 393216 |
Author:旭东 |
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Description: 关于同步异步电路设计的介绍和重点分析,最后给出示例，表示分析描述-Synchronous Asynchronous circuit design on the presentation and focus of analysis, and finally gives examples that analyze and describe Platform: |
Size: 13312 |
Author:qing |
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Description: 很实用详细的HDL编程艺术技巧，是英文版的。包括触发器、同步、异步电路设计的等。-HDL programming in detail very practical artistic skills, is in English. Including flip-flops, synchronous and asynchronous circuit design and so on. Platform: |
Size: 227328 |
Author:杰夫 |
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Description: 异步FIFO是一种先进先出的电路，在异步电路中，由于时钟之间周期和相位完全独立，因而数据丢失概率不为零。如何设计一个高可靠性、高速异步的FIFO是一个难点，本代码介绍了一种解决方法。-Asynchronous FIFO is a kind of advanced first out circuit, in asynchronous circuit, as the clock cycle and phase between full independence, thus data loss probability is not zero. How to design a high reliability, high speed asynchronous FIFO is a difficulty, this code introduced a kind of solution.
Platform: |
Size: 3072 |
Author:王国庆 |
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Description: 基于verilog的异步驱动电路的设计传输实现与研究详解-Verilog-based asynchronous driver circuit design to achieve transfer and research Detailed Platform: |
Size: 2048 |
Author:吴进强 |
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Description: 本实验目标是利用FPGA逻辑资源，编程设计实现一个串行通用异步收发器。实验器件为“创新综合实验平台”上集成的Altera NIOSII开发板，FPGA芯片型号为EP1C12F324C8。电路设计采用VHDL硬件描述语言编程实现，开发软件为QuartusII6.0。-The goal is to use the FPGA logic resources, programming design realize a serial general asynchronous transceiver. The experiment device for "innovation comprehensive experimental platform" on integrated Altera NIOSII development board, FPGA the chip for EP1C12F324C8. Circuit design by VHDL language programming realize hardware description, the development of software for the QuartusII6.0.
Platform: |
Size: 394240 |
Author:郭晓阳 |
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Description: 异步FIFO是一种先进先出电路，可以有效解决异步时钟之间的数据传递。通过分析异步FIFO设计中的难点，以降低电路中亚稳态出现的概率为主要目的，大大提高工作频率和资源利用率。-Asynchronous FIFO is an advanced circuit that can effectively solve the data transfer between asynchronous clock. Through the analysis of the difficulties in asynchronous FIFO design, the probability of the Central Asian steady state is the main purpose, greatly improving the working frequency and resource utilization.. Platform: |
Size: 3072 |
Author:高浚玮 |
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