Description: altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II Platform: |
Size: 8863744 |
Author:刘吉 |
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Description: pci core altera fpga pci开发设计资料-pci core altera fpga development of design information pci Platform: |
Size: 156672 |
Author:zhouhong |
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Description: altera Quartus II FSM使用
可設定時間波形，手動調整波形頻率。
(含電路)
-altera Quartus II FSM can be set using the time waveform, manually adjust the frequency waveform. (With circuit) Platform: |
Size: 114688 |
Author:陳小龍 |
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Description: FPGA开发入门的Verilog HDL程序2---梁祝音乐播放,真实可用，验证通过，工程环境为Altera Quartus II
-Introduction to the Verilog HDL FPGA development process 2 --- Butterfly music player, the real available, verified by the project environment for the Altera Quartus II Platform: |
Size: 301056 |
Author:renyong0801 |
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Description: 利用Nios Ⅱ软核处理器，以Altera公司的UP3开发板为硬件平台，以Quartus II、Quartus ID为软件开发平台，设计一个电子钟，实现下列系统功能：
（1）在液晶屏上显示时间、日期、状态提示；
（2）利用4个按键对时间（时分秒）、日期（年月日）进行设置；
（3）利用一个LED灯指示当前设置状态；-The use of soft-core processor, Nios Ⅱ to Altera s UP3 development board as the hardware platform to Quartus II, Quartus ID for software development platform, design a clock Platform: |
Size: 6460416 |
Author:Emma |
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Description: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal. Platform: |
Size: 182272 |
Author:张保平 |
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Description: altera官方网站上资料的示例代码Quartus II Software Design Series Foundation-altera official website information sample code Quartus II Software Design Series Foundation Platform: |
Size: 18641920 |
Author:jiangwen |
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Description: 该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据，使用ＶｅｒｉｌｏｇＨＤＬ语言编写，在ＱｕａｒｔｕｓＩＩ开发环境下验证。-The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compiling the whole code the user should open mem.v file and change lpm_ram declarations in RAM module and lpm_rom declarations in ROM module into such that are suitable for a particular producer and scheme. There also may appear the necessity of converting .mif files used to memory initialization. The Memory Initialization File is serviced by the Quartus II environment developed by Altera. Platform: |
Size: 18432 |
Author:submars |
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Description: 附录 光盘说明
本书附赠的光盘包括各章节实例的设计工程与源码，所有工程在下列软件环境下运行通过：
? Windows XP SP2
? MATLAB
? Altera Quartus II
? synplify8.4
? modelsim_ae6.1
光盘目录与实例名称的对应关系如下：
cht02文件夹中存放的是书中第2章中的例子，读者可以将一些简单例子的代码
拷贝到MATLAB命令窗口进行运行，也可以把一些复杂的例子做成一个单独
的*.m文件然后运行、调试(要将每行前的“>>”删除)。
cht04文件夹存放的是书中第4章的例子代码。每个例子都建立了一个单独的文件夹，
除了存放与例子相关的代码外，还对各个例子建立了Quartus II工程，编制了仿真测试向量，并对例子进行了编译、综合、布局布线和时序仿真。
cht05文件夹中存放的是一个完整的正弦波频率产生的例子，即书中5.4.1节中的代码，
读者可以应用这些代码建立自己的项目，按照书中介绍的方法，获得完整的项目设计经验。
注意事项：
光盘中的源代码为作者编写，并调试通过，有兴趣的读者可以在此基础上进行二次开发，但请不要用作商业用途。
-CD-ROM Appendix Description
The book comes with a CD-ROM includes examples of various sections of the design engineering and source code, all works in the following software environment to run through:
? Windows XP SP2
? MATLAB
? Altera Quartus II
? Synplify8.4
? Modelsim_ae6.1
CD-ROM directories and examples of correspondence between the names is as follows:
cht02 folders stored in the book are Chapter 2 of the examples, readers may be some simple code examples
Copy to the MATLAB command window to run, you can put some examples of the complex into a single
And the*. m files to run, debug (to each line before the ">>" delete).
cht04 folders stored in the book are examples of Chapter 4 code. Examples of each set up a separate folder,
In addition to the storage associated with the example code, but also examples of each set up a Quartus II project, the preparation of the simulation test vectors, and examples have been compiled, integrated, p Platform: |
Size: 6961152 |
Author:吕成林 |
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Description: 在ALTERA的DE2开发板上做的关于HOST_MOUSE的例子，基于Quartus II 和SOPC Builder以及Nios II IDE平台所完成！-ALTERA development in the DE2 board to do on HOST_MOUSE example, based on the Quartus II and SOPC Builder and Nios II IDE platform completed! Platform: |
Size: 1874944 |
Author:liguoyin |
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Description: 在ALTERA的DE2板子上做的一个读写SD卡的例子，基于QUARTUS II ,SOPC BUILDER ,Nios II IDE实现的，从SD卡读写东西-The DE2 board in ALTERA do an SD card reader example, based on the QUARTUS II, SOPC BUILDER, Nios II IDE achieved something from the SD card reader Platform: |
Size: 1816576 |
Author:liguoyin |
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Description: quartus II 软件入门和进阶，是《ALtera fpga_cpld 设计》（基础篇）-quartus II software, introductory and advanced, is " ALtera fpga_cpld design" (Basics) Platform: |
Size: 22313984 |
Author:孙楠 |
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Description: 包括三个文档:
1.基于Altera Quartus II 的模块化设计应用
2.基于Xilinx ISE的的模块化设计示例
3.模块化设计方法的设计流程-Consists of three documents: 1. Based on Altera Quartus II modular design applications 2. Xilinx ISE based on the modular design of Example 3. Modular Design for design process Platform: |
Size: 252928 |
Author:Joseph |
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Description: Altera Quartus II 10.1最新破解文件，本人一直独家专用，X86和X64都有。-Altera Quartus II 10.1 latest crack file, I have been exclusively dedicated, X86 and X64 have. Platform: |
Size: 769024 |
Author:sunnic-atom |
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