Description: 闹钟系统，用VHDL语言进行编码，
请多指教，可能不是很好-alarm system, using VHDL coding, please enlighten, may not be very good Platform: |
Size: 2945 |
Author:jinlong |
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Description: 闹钟系统，用VHDL语言进行编码，
请多指教，可能不是很好-alarm system, using VHDL coding, please enlighten, may not be very good Platform: |
Size: 3072 |
Author:jinlong |
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Description: 包含了VHDL语言的100个例子，如交通灯控制器，空调系统有限状态自动机，FIR滤波器，五阶椭圆滤波器，闹钟系统的控制-VHDL language contains 100 examples, such as traffic light controllers, air-conditioning systems finite state automata, FIR filter, the fifth-order elliptic filter, alarm system control Platform: |
Size: 320512 |
Author:ttang |
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Description: 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。
实验平台：
1. 一台PC机；
2. MAX+PLUSII10.1。
Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report Platform: |
Size: 425984 |
Author:盼盼 |
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Description: l、设计用于竞赛的四人抢答器，功能如下：
(1) 有多路抢答器，台数为四；
(2) 具有抢答开始后20秒倒计时，20秒倒计时后无人抢答显示超时，并报警；
(3) 能显示超前抢答台号并显示犯规警报；
(4) 能显示各路得分，并具有加、减分功能；
2、系统复位后进入抢答状态，当有一路抢答键按下时，该路抢答信号将其余各路抢答封锁，同时铃声响，直至该路按键松开，显示牌显示该路抢答台号。
3、用VHDL语言设计符合上述功能要求的四人抢答器，并用层次设计方法设计该电路
-l, designed for Answer four contests, and features are as follows: (1) Answer the way how, and the number to four (2) Answer 20 seconds after the beginning of the countdown, countdown to 20 seconds after the Answer shows no overtime, and report to the police (3) can show in advance Answer Desk No. foul alarm and display (4) can display various scoring with Canada, by sub-function 2, the system reset after entering the Answer state, all the way when pressing the Answer key , the signals will be the rest of the way each Answer Answer blockade, ring tones at the same time, release the button until the road, the road signs showing the number Answer Desk. 3, using VHDL language design meets the functional requirements of the above Answer four devices, and design method-level design of the circuit Platform: |
Size: 305152 |
Author:hugh |
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Description: 基于单片机的DS18B20温度采集系统
实时温度采集
具有报警功能-DS18B20 temperature based on single-chip real-time acquisition system with alarm function of temperature acquisition Platform: |
Size: 151552 |
Author:zhouhongxi |
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Description: 用于模仿密码锁的工作过程。完成密码锁的核心控制功能。可实现数码输入、清除、退位、设置密码、错误提示、系统报警、解除报警、系统关闭等功能。-Used to imitate the work of the code lock process. Locks achieve the core control functions. Digital input can be achieved, clear, step down, set a password, error message, the system alarm, lift the alarm, turn off the functions of the system. Platform: |
Size: 13312 |
Author:胡婕 |
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Description: 密码锁控制器
设计一个密码锁，平时处于等待状态。管理员可以设置或更该密码。如果不预置密码，
密码缺省为“6666”。用户如果需要开锁，按相应的按键进入输入密码状态，输入4位
密码，按下确定键后，若密码正确，锁打开，若密码错误，将提示密码错误，要求重
新输入，三次输入都错误，将发出报警信号。报警后，只有管理员作相应的处理才能
停止报警。用户输入密码时，若输入错误，在按下确定键之前，可以通过按取消键重
新输入。正确开锁后，用户处理完毕后，按下确定键，系统回到等待状态。系统操作
过程中，只要密码锁没有打开，如果1 分钟没有对系统操作，系统回到等待状态。
-Password lock controller
Designed a password lock, waiting in a normal status. Administrators can set up or the password. If you do not preset password,
Default password is "6666." If you need to unlock the user, according to the corresponding status button to enter a password, type 4
Password, press OK, if the password is correct, open the lock, if the wrong password, wrong password will be prompted to request re-
New inputs, the importation of all three errors, will issue a warning signal. Alarm, only the administrator can deal with accordingly
Stop the alarm. Users to enter a password, if the input error, identified in the press before the key can be canceled by pressing the key re-
New input. Unlock right, the user after the treatment, press OK, the system back to waiting status. System Operator
As long as there is no open locks, 1 minutes, if not on the system operation, system status back to wait. Platform: |
Size: 1024 |
Author:Jane |
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Description: 主要介绍闹钟系统的整体组装的源程序与主程序-Alarm system introduces a whole assembly with the main program source code. Platform: |
Size: 4096 |
Author:小小深 |
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Description: 用VHDL实现了电梯的模拟程序，实现了自动判断楼层，然后根据客户需求和楼层最近原则，实现自动判断上下行，还有报警，强制开门等功能-Achieved using VHDL elevator simulation program, to determine the realization of an automatic floor, and then based on the principle of demand and the floor recently, automatically determine the next line, as well as alarm, forced open the door and other features ~ ~ Platform: |
Size: 1024 |
Author:董灏 |
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Description: 本文档采用VHDL语言编写了一个数字时钟的程序，该数字时钟采用24小时制计时，可以实现整点报时，时间设置，闹钟等功能。最小分辨率为1秒。-VHDL language in this document using a digital clock to prepare the procedure, the digital clock 24-hour time system, you can bring the whole point of time, time settings, alarm clock functions. Minimum resolution of 1 second. Platform: |
Size: 680960 |
Author:cindy |
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Description: （1）用VHDL语言编写程序，在EDA实验板上实现
（2）能正常计时。显示模式分为两种，即24小时制和12小时制。其中12小时制须显示上，下午（用指示灯显示）。时，分，秒都要显示。
（3）. 手动校准电路。用一个功能选择按钮选择较时，分功能，用另一个按钮调校对应的时和分的数值。
用VHDL语言编写程序，在EDA实验板上实现
（4） 整点报时。
（5）. 闹钟功能。
（6）．秒表功能。-(1) using VHDL language program, in the EDA experiments on-board implementation (2) to resume normal time. Display mode is divided into two kinds, namely, a 24-hour system and 12-hour clock. Including 12-hour clock to be displayed on the afternoon (with light display). Hours, minutes and seconds to be displayed. (3). Manual calibration circuit. With a select button to choose a more functional hours, minutes functions, with another button to adjust the corresponding time and sub-values. Using VHDL language programs, in the EDA experiments on-board implementation (4) The whole point timekeeping. (5). Alarm. (6). Stopwatch function. Platform: |
Size: 4096 |
Author:malon |
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Description: vhdl source code of fire detection system/fire alarm system especially for high rise building?
This among the requirement :-
according to my "fire detection system for tall building" project by using Spartan 3E FPGA, the vhdl program need to include all of dis specification:-
First of all, we ll put sensor/smoke detector each floor in the tall building.
1) alarm ll activated if the sensor/smoke detector sense a fire
2)at the same time, the actuator will activate in order to control such a elevator and any other machines in the building.
3)the controller will display which floor caught by fire and the sensor/smoke detector initial or current temperature.
4)If there is false alarm, we can stop it by push the reset button .-vhdl source code of fire detection system/fire alarm system especially for high rise building?
This is among the requirement :-
according to my "fire detection system for tall building" project by using Spartan 3E FPGA, the vhdl program need to include all of dis specification:-
First of all, we ll put sensor/smoke detector each floor in the tall building.
1) alarm ll activated if the sensor/smoke detector sense a fire
2)at the same time, the actuator will activate in order to control such a elevator and any other machines in the building.
3)the controller will display which floor caught by fire and the sensor/smoke detector initial or current temperature.
4)If there is false alarm, we can stop it by push the reset button . Platform: |
Size: 1024 |
Author:subin |
Hits:
Description: l、设计用于竞赛的四人抢答器，功能如下： (1) 有多路抢答器，台数为四； (2) 具有抢答开始后20秒倒计时，20秒倒计时后无人抢答显示超时，并报警； (3) 能显示超前抢答台号并显示犯规警报； (4) 能显示各路得分，并具有加、减分功能； 2、系统复位后进入抢答状态，当有一路抢答键按下
[qingdaqi.rar] - 四路抢答器，超时报警，提前抢答报警，计分等
-l, designed for race four Responder, functions as follows: (1) a number of road Responder, Taiwan, the number is four (2) has the answer in 20 seconds after the beginning of the countdown, 20 seconds after the countdown show no answer in overtime, and alarm (3) can show answer in advance and display the foul alarm station number (4) to display scores from various quarters, and with addition, subtraction, sub-functions 2, enter the answer in the state after a system reset, when a key is pressed all the way Responder [qingdaqi.rar]- Quad Responder, time-out alarm, alarm answer in advance, namely, classification Platform: |
Size: 2048 |
Author:杰克 |
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Description: 用Veriolg编写的数字钟实验，能进行时、分、秒计时的二十四小时制的数字钟，并具有定时与闹钟功能。-Digital clock with Veriolg written test, can be hours, minutes, seconds, the system timing clock digital clock and alarm clock with timing and function. Platform: |
Size: 2497536 |
Author: |
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Description: 基于FPGA的电子万年历，此电子万年历系统主要有8个模块分别设计1. 主控制模块 maincontrol
2. 时间及其设置模块 timepiece_main
3. 时间显示动态位选模块 time_disp_select
4. 显示模块 disp_data_mux
5. 秒表模块 stopwatch
6. 日期显示与设置模块 date_main
7. 闹钟模块 alarmclock
8. 分频模块 fdiv
-FPGA-based electronic calendar, the electronic calendar system, there are 8 modules are designed for 1. The main control module maincontrol 2. Time and the setup module timepiece_main 3. Time Choice module displays dynamic time_disp_select 4. Display Module disp_data_mux 5. Stopwatch module stopwatch 6. Date display and set the module date_main 7. alarm module alarmclock 8. fdiv frequency module Platform: |
Size: 1024 |
Author:黄枫 |
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Search - ALARM SYSTEM vhdl