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[source in ebook] 63535312DCTofJPEG

Description: 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
Platform: | Size: 2048 | Author: jiang | Hits:

[Crack Hack] systemcaes_latest.tar

Description: 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
Platform: | Size: 83968 | Author: lxc | Hits:

[Program doc] Rijndael

Description: AES USING PICOBLAZE CODE
Platform: | Size: 17408 | Author: sruthi | Hits:

[Crack Hack] aes

Description: 其程序是用xilinx环境下编写的，风格是Verilog，请大家提意见。-The program is written using xilinx environment, style Verilog, please comments.
Platform: | Size: 3072 | Author: 郝志刚 | Hits:

[VHDL-FPGA-Verilog] aes-vhdl

Description: 使用vhdl语言实现aes（rijndael 算法），程序整体封装成为一个package，方便调用-Using vhdl language aes (rijndael algorithm), the program as a whole package as a package, easy call
Platform: | Size: 7168 | Author: Bruce Lee | Hits:

[Software Engineering] IJCSI-9-4-3-354-360_2

Description: fpga the aes algorithme by using vhdl
Platform: | Size: 696320 | Author: arrag | Hits:

[Software Engineering] Sources

Description: aes cipher text using vhdl.enjoy it for fr-aes cipher text using vhdl.enjoy it for free
Platform: | Size: 7168 | Author: geuston | Hits:

[VHDL-FPGA-Verilog] des_vhdl_code

Description: decription aes using vhdl code
Platform: | Size: 140288 | Author: dani.hassoun | Hits:

[Other] aes_128

Description: aes encrypyion using vhdl, coding and decoding
Platform: | Size: 56320 | Author: olufemi | Hits:

[File Format] AES-FPGA

Description: 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware uation.
Platform: | Size: 191488 | Author: Eric | Hits:

[Other] sbox-_proposed

Description: Implementation of AES S BOX using VHDL
Platform: | Size: 5120 | Author: Rajasekar | Hits:

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