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[
VHDL-FPGA-Verilog
]
ADCINT
Description:
模数转换的一个工程---包括vhdl源程序和编译后产生的相关文件-Analog-digital conversion of a project- including VHDL source code and compile the relevant documents after
Platform:
|
Size:
172032
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Author:
吴晨光
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