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Description: 一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！
The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires.
FEATURES:
· Compatible with Motorola’s SPI specifications
· Enhanced M68HC11 Serial Peripheral Interface
· 4 entries deep read FIFO
· 4 entries deep write FIFO
· Interrupt generation after 1, 2, 3, or 4 transferred bytes
· 8 bit WISHBONE RevB.3 Classic interface
· Operates from a wide range of input clock frequencies
· Static synchronous design
· Fully synthesizable
-a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Platform: |
Size: 473099 |
Author: Jack |
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Description: 一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！
The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires.
FEATURES:
· Compatible with Motorola’s SPI specifications
· Enhanced M68HC11 Serial Peripheral Interface
· 4 entries deep read FIFO
· 4 entries deep write FIFO
· Interrupt generation after 1, 2, 3, or 4 transferred bytes
· 8 bit WISHBONE RevB.3 Classic interface
· Operates from a wide range of input clock frequencies
· Static synchronous design
· Fully synthesizable
-a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Platform: |
Size: 473088 |
Author: Jack |
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Description: j2ee et la liaison avec une base de donnée ace-j2ee et la liaison avec une base de donnée acess
Platform: |
Size: 391168 |
Author: aziza |
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Description: ACE网络组件使用实例。本源码分为两个部分，分为用ACE写的服务端和用ACE写的客户端。-Network components using the example of ACE. The source is divided into two parts, divided into services with ACE client to write and write with ACE client.
Platform: |
Size: 992256 |
Author: gpc |
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Description: 最短的路径依赖关系提取
我们提出了一个新颖的方法来提取关系，根据观察断言之间的关系之间的两个命名实体在同一个句子1所需的信息通常是由两个实体之间的依赖关系图中的最短路径捕获。实验上提取的ACE（自动内容抽取）报纸语料表明，新的最短路径依赖内核外执行最近的做法，根据去依赖树内核顶层的关系-We present a novel approach to relation extraction, based on the observation that the information required to assert a rela-tionship between two named entities in the same sentence is typically captured by the shortest path between the two entities in the dependency graph. Experiments on extracting top-level relations from the ACE (Automated Content Extraction) newspaper corpus show that the new shortest path dependency kernel out-performs a recent approach based on de-pendency tree kernels
Platform: |
Size: 133120 |
Author: xz |
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