Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - A/D VERILOG

Search list

[Other resource] adc

Description: 编写verilog代码 利用实验箱上的A/D芯片完成模数转换。输入电压由实验箱提供，其幅值在0~5V间变化，由电位器控制。输出信号显示输入的模拟电压值，由数码管显示为2位BCD码的形式。
Platform: | Size: 22228 | Author: Ericwhu | Hits:

[Embeded-SCM Develop] tlc2543

Description: 12位串行A/D转换芯片TLC2543的驱动程序--Driver program for 12-bit serial A/D conversion chip TLC2543.
Platform: | Size: 1024 | Author: 李罗 | Hits:

[VHDL-FPGA-Verilog] 数据结构c描述习题集答案

Description: 减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input/output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting/0 : Stop counting); Updown : dollars several self-Canada/reduction Operational control (1 : Since the plus/0 : Since decrease); load_d
Platform: | Size: 111616 | Author: tutu | Hits:

[Other] 2005_LinuxKernelDevelopment[2ED]_RobertLove

Description: The Linux kernel is one of the most interesting yet least understood open-source projects. It is also a basis for developing new kernel code. That is why Sams is excited to bring you the latest Linux kernel development information from a Novell insider in the second edition of Linux Kernel Development. This authoritative, practical guide will help you better understand the Linux kernel through updated coverage of all the major subsystems, new features associated with Linux 2.6 kernel and insider information on not-yet-released developments. You ll be able to take an in-depth look at Linux kernel from both a theoretical and an applied perspective as you cover a wide range of topics, including algorithms, system call interface, paging strategies and kernel synchronization. Get the top information right from the source in Linux Kernel Development. -The Linux kernel is one of the most interest ing yet least understood open-source projects . It is also a basis for developing new kernel cod e. That is why Sams is excited to bring you the lat est Linux kernel development information from a Novell insider in the second edition of Linux K ernel Development. This authoritative. practical guide will help you better understan d the Linux kernel through updated coverage of a ll the major subsystems, new features associated with a Linux 2.6 kernel nd insider information on not-yet-released de velopments. You'll be able to take an in-depth lo ok at Linux kernel from both a theoretical and an applied perspective as you cover a wide range of topics, including algorithms, system call interface. paging strategies and kernel synchronization . Get
Platform: | Size: 1334272 | Author: 李中伟 | Hits:

[Embeded-SCM Develop] dff_UDP

Description: verilog实现，UDP描述带有异步复位的正边沿触发D触发器，test测试通过-verilog achieve, UDP asynchronous reset with a description of the fringe is triggered D flip-flop, test test pass
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] A-to-D-VerilogHDL

Description: 在硬體上將十進制轉二進制，不需要使用加法器的運算方式，大大減少運算的時間。-In terms of hardware decimal to binary will be no need to use adder computing the way, greatly reducing the computing time.
Platform: | Size: 1024 | Author: 旻倫 | Hits:

[VHDL-FPGA-Verilog] DCT

Description: 用verilog语言实现DCT编解码 附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
Platform: | Size: 65536 | Author: 周韧研 | Hits:

[VHDL-FPGA-Verilog] dac

Description: DAC converter design with Verilog code and testbench
Platform: | Size: 527360 | Author: 田磊 | Hits:

[SCM] adc

Description: 编写verilog代码 利用实验箱上的A/D芯片完成模数转换。输入电压由实验箱提供，其幅值在0~5V间变化，由电位器控制。输出信号显示输入的模拟电压值，由数码管显示为2位BCD码的形式。-The preparation of Verilog code box on the use of experimental A/D chip to complete analog-digital conversion. Input voltage provided by the experimental box, and its amplitude in the 0 ~ 5V between changes in control by potentiometer. Output signal shows that the value of analog voltage input from a digital display for two BCD code of the form.
Platform: | Size: 22528 | Author: Ericwhu | Hits:

[VHDL-FPGA-Verilog] TLC5510_VHDL

Description: 基于VHDL语言，实现对高速A/D器件TLC5510控制-Based on the VHDL language, to achieve high-speed A/D device control TLC5510
Platform: | Size: 1024 | Author: huangsong | Hits:

[Other] Verilog

Description: verilog的简要教程 基本逻辑门，例如a n d、o r和n a n d等都内置在语言中。 • 用户定义原语（ U D P）创建的灵活性。用户定义的原语既可以是组合逻辑原语，也可以 是时序逻辑原语。 • 开关级基本结构模型，例如p m o s 和n m o s等也被内置在语言中。-Verilog tutorial briefly the basic logic gates, such as and, or and NAND are built in the language. • user-defined primitives (UDP) to create flexibility. User-defined primitives are the combinational logic can be the original language may also be a temporal logic primitives. • The basic structure of switch-level models, such as PMOS and NMOS are also being built in the language.
Platform: | Size: 4169728 | Author: 阿春 | Hits:

[VHDL-FPGA-Verilog] analogue-digi-ana-converter

Description: design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.
Platform: | Size: 1398784 | Author: ak | Hits:

[VHDL-FPGA-Verilog] max197

Description: verilog编写的状态机控制A/D芯片MAX197正常工作-use verilog write the state machine which is used to meke the A/D chip working!
Platform: | Size: 1024 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] Verilogexample

Description: verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci Number Generator.8.A NAND Latch.9.The Seed-Number Generator-verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6 . The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci Number Generator.8.A NAND Latch.9.The Seed-Number Generator ....
Platform: | Size: 30720 | Author: vkiy | Hits:

[VHDL-FPGA-Verilog] SPI

Description: design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.-design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.
Platform: | Size: 1024 | Author: weichenghao | Hits:

[VHDL-FPGA-Verilog] 20110126113917873

Description: A/D转换芯片TLC2543的verilog编程，根据TLC5243的datasheet编写，程序简单，结构清晰，可以借鉴应用-A/D converter chip TLC2543 the verilog programming
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] AD9708

Description: AD9708是高速AD转换芯片，采用VHDL实现10MSPS高速AD数据采集-AD9708 is high speed a/d conversion chip,10MSPS,using VHDL
Platform: | Size: 851968 | Author: yu_hai_yang | Hits:

[VHDL-FPGA-Verilog] Advanced-Digital-Design-with-the-Verilog-HDL-CODE.

Description: 《Verilog HDL高级数字系统设计》（Michael D. Ciletti著） Verilog HDL源代码-" Verilog HDL Advanced Digital System Design" (Michael D. Ciletti a) Verilog HDL source code
Platform: | Size: 1070080 | Author: 曹氏 | Hits:

[Industry research] DLL-verilog

Description: verilog model of a D-verilog model of a DLL
Platform: | Size: 10240 | Author: aida yua | Hits:

[VHDL-FPGA-Verilog] test_ADC

Description: verilog 数模转换程序，包括AD与DA，AD能够对于波形的数值进行输出，使用的是ego1开发板(transition of A/D signal)
Platform: | Size: 12637184 | Author: 白珑 | Hits:
« 12 3 4 »

CodeBus www.codebus.net