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Description: 可编程器件大厂Xilinx提供的高速多状态编码8b_10b编码器，可直接使用在Xilinx公司器件的设计上-Xilinx programmable device manufacturers to provide high-speed multi-state coding 8b_10b encoder, direct access to the Xilinx devices on the design
Platform: |
Size: 179576 |
Author: 宋云成 |
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Description:
vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
Encoded data output
10-bit parallel encoded output valid 1 clock later
Decoder:
8b/10b Decoder (file: 8b10b_dec.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
10-bit parallel encoded data input
Asynchronous active high reset initializes all logic
Decoded data, disparity and KO outputs
8-bit parallel unencoded output valid 1 clock later
Platform: |
Size: 73116 |
Author: 聂样 |
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Description: 可编程器件大厂Xilinx提供的高速多状态编码8b_10b编码器，可直接使用在Xilinx公司器件的设计上-Xilinx programmable device manufacturers to provide high-speed multi-state coding 8b_10b encoder, direct access to the Xilinx devices on the design
Platform: |
Size: 179200 |
Author: 宋云成 |
Hits:
Description:
vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
Encoded data output
10-bit parallel encoded output valid 1 clock later
Decoder:
8b/10b Decoder (file: 8b10b_dec.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
10-bit parallel encoded data input
Asynchronous active high reset initializes all logic
Decoded data, disparity and KO outputs
8-bit parallel unencoded output valid 1 clock later -VHDL prepared, 8b-10b codec design Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
Platform: |
Size: 72704 |
Author: 聂样 |
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Description: 8b_10b encoder/decoder
Platform: |
Size: 69632 |
Author: dinesh |
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Description: 光纤通信8B_10b编码；8B/10B 编码顾名思义，即将发送方的 8bit 并行信号通过特殊的映射变成 10bit 并行信
号
Platform: |
Size: 1024 |
Author: L |
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Description: 8b_10b编码解码源码以及相应的测试文件基于14.2-8b_10b codec source code and the corresponding test file is based on 14.2
Platform: |
Size: 570368 |
Author: mayunfeng |
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Description: 8B_10B译码程序已通过验证，程序波形与输出没有问题-8B_10B decoding program has been validated, the program is no problem with the output waveform
Platform: |
Size: 1024 |
Author: 陈永举 |
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Description: 8B10B 编解码实现 用VHDL实现的-8B10B encoding decoding
Platform: |
Size: 72704 |
Author: andi |
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Description: 本文重点研究了高速8b／10b解码器的设计与实现，在详细介绍了解码原理及
多种传统解码方案的基础上，采用流水线结构设计了高速8b／10b解码器。通过
仔细分析传统解码器的不足，精心设计流水线结构及触发器在关键路径上的插入
点，使得所设计电路的速度比传统解码器有了较大的提升。-This paper focuses on the 8b／l 0b decoder，including the decoding principles and
a variety of decoding schemes which will be analyzed and compared in this paper．
With careful analysis of conventional decoder，pipelined decoder is well designed and
insertion points on the critical path are carefully selected．
Platform: |
Size: 9962496 |
Author: 梧桐雨 |
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Description: 8B_10B编码器FPGA设计,平台上验证，结果可用。(Design of FPGA encoder 8B_10B,reading out crc after calculating the value.)
Platform: |
Size: 1024 |
Author: dsadgag
|
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