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[VHDL-FPGA-Verilogwatch

Description: 用VHDL设计实现秒表功能:秒表功能包括开始/暂停键和清零键,精度要达到0.01秒,所以计数显示共有八个数码管,而每个数码管又有八个管脚,因此采用扫描显示的方法,减少管脚数量。时钟脉冲由最低位给入,采用异步方式驱动更高位的计数,时钟频率应该为100Hz,通过数码管显示,共有八个数码管,所以扫描频率应在100Hz的8倍以上。(付按键消抖代码)-VHDL design with a stopwatch functions: stopwatch features include Start/PAUSE button and the Clear, 0.01 seconds to achieve accuracy, so count showed a total of eight digital tube, each of the digital control and eight-pin, so the use of scan ways to reduce the number of pins. Clock pulse from the lowest to the income, the use of asynchronous drive higher bit count, the clock frequency should be 100Hz, digital display, a total of eight digital tube, the scanning frequency should be 8 times higher than 100Hz. (Pay button Buffeting code elimination)
Platform: | Size: 27648 | Author: 李月 | Hits:

[VHDL-FPGA-Veriloglock

Description: 设计一个8位串行数字密码锁控制电路 -Design an 8-bit serial digital code lock control circuit
Platform: | Size: 1024 | Author: 冷与 | Hits:

[VHDL-FPGA-VerilogEP2C5T-control-8-seg7led

Description: 使用EP2C5T144编译的控制8位数码管显示电路的VHDL源码-EP2C5T144 compiled using 8-bit digital display control circuit VHDL source code
Platform: | Size: 1024 | Author: 海鹰 | Hits:

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