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[VHDL-FPGA-Verilog7vhdl

Description: 16 进制段位数码译码扫描显示,用VHDL编写计数器并完成计数显示-16-band digital decoding scan revealed Dan, using VHDL to prepare and complete the count of counter display
Platform: | Size: 61440 | Author: wang | Hits:

[SCM7seg

Description: 利用8051控制8个七段显示器,采用分时多任务方式显示,显示内容为时钟计数。-8051 to control the use of paragraph 8 displays, using time-sharing multi-task display, showing the content for the clock count.
Platform: | Size: 71680 | Author: jonathan lee | Hits:

[Other7 seg 4#.X

Description: count up/down with dspic 24fj128 simulation with proteus
Platform: | Size: 51200 | Author: naser_rezai | Hits:

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