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Description: vhdl语言实现的16乘16的点阵显示设计代码,调试通过,可借鉴
Platform: | Size: 298934 | Author: yj | Hits:

[VHDL-FPGA-Verilog16multi16

Description: vhdl语言实现的16乘16的点阵显示设计代码,调试通过,可借鉴-VHDL language to achieve the 16 by 16 dot matrix display design code, debug is passed, can learn from
Platform: | Size: 299008 | Author: yj | Hits:

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