Description: 该源码为8位乘法器的VHDL语言描述，由一个8位右移寄存器，2个4位加法器例化成8位加法器，一个16位数据锁存器构成。采用移位相加的方式，从被乘数的低位开始，与乘数的每个位移位相加求和。最后实现其乘法器功能。-The source code for the 8-bit multiplier in VHDL language to describe, from an 8-bit right shift register, two 4-bit adder example into 8-bit adder, a 16-bit data latch form. Using the sum of the shift, from a low starting multiplicand, the multiplier for each bit shift and summed. Finally, to achieve its multiplier function. Platform: |
Size: 393216 |
Author:feng |
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Description: Design, simulate and synthesize a 16-bit integer multiplier using only one 4-bit adder. This 4-bit adder is to be made with four 1-bit adders as components. The coding is in VHDL.-Design, simulate and synthesize a 16-bit integer multiplier using only one 4-bit adder. This 4-bit adder is to be made with four 1-bit adders as components. The coding is in VHDL. Platform: |
Size: 2048 |
Author:zero chen |
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