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[VHDL-FPGA-Verilog16-1MUX

Description: 16 down to 1 Multiplexer in Vhdl
Platform: | Size: 65536 | Author: Abdullah | Hits:

[VHDL-FPGA-VerilogMuxDemux_E1_E3

Description: E3 -Mux / Demux - Multiplexer of 16 E1 Channels-E3 -Mux / Demux - Multiplexer of 16 E1 Channels
Platform: | Size: 7168 | Author: qi | Hits:

[VHDL-FPGA-VerilogThe-VHDL-various-basic-code

Description: VHDL的各种基本代码 包括4选1,8选1多路选择器,8位全加器,加1减1计数器,序列检测器,异步清零16位加减可控计数器,数码管扫描程序,双2选1,状态机等基本程序!-VHDL basic code including 4 election 1,8 to 1 multiplexer selector, 8-bit full adder, plus 1 minus 1 counter sequence detector, asynchronous clear 16 plus or minus controllable counter, digital tube scanner , dual 2 1 state machine program!
Platform: | Size: 3696640 | Author: ai | Hits:

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