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Description: 1-wire\"从机\"模拟程序, 不是主机,1-wire的主机模拟程序网上很多.使用mega88模拟DS1990A芯片时序, 再加上模拟主机就可以搭建不使用DALASI芯片而使用1-wire协议的系统.编译IAR for AVR 4.20.
Platform: |
Size: 6007 |
Author: 杨成双 |
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Description: The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control
and data transfer communication between ICs.
Some of the features of the I2C bus are:
• Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A
12V supply line (500mA max.) for powering the peripherals often may be present.
• Each device connected to the bus is software addressable by a unique address and simple
master/ slave relationships exist at all times masters can operate as master-transmitters or as
master-receivers.
• The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data
corruption if two or more masters simultaneously initiate data transfer systems.
• Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard
mode or up to 400 KBit/s in the fast mode.
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Size: 788781 |
Author: lu |
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Description: VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
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Size: 65536 |
Author: 阿飞 |
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Description: This program accesses a SPI EEPROM using polled mode access. The F12x MCU is configured in 4-wire Single Master Mode, and the EEPROM is the only slave device connected to the SPI bus. The read/write operations are tailored to access a Microchip 4 kB EEPROM-This program accesses a SPI EEPROM using polled mode access. The F12x MCU is configured in 4-wire Single Master Mode, and the EEPROM is the only slave device connected to the SPI bus. The read/write operations are tailored to access a Microchip 4 kB EEPROM
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Size: 5120 |
Author: slowlykiss |
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Description: // This program accesses a SPI EEPROM using polled mode access. The F06x MCU
// is configured in 4-wire Single Master Mode, and the EEPROM is the only
// slave device connected to the SPI bus. The read/write operations are
// tailored to access a Microchip 4 kB EEPROM 25LC320. The relevant hardware
// connections of the F06x MCU are shown here:
Platform: |
Size: 7168 |
Author: 蓝天 |
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Description: 1-wire"从机"模拟程序, 不是主机,1-wire的主机模拟程序网上很多.使用mega88模拟DS1990A芯片时序, 再加上模拟主机就可以搭建不使用DALASI芯片而使用1-wire协议的系统.编译IAR for AVR 4.20.-1-wire
Platform: |
Size: 6144 |
Author: 杨成双 |
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Description: The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control
and data transfer communication between ICs.
Some of the features of the I2C bus are:
• Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A
12V supply line (500mA max.) for powering the peripherals often may be present.
• Each device connected to the bus is software addressable by a unique address and simple
master/ slave relationships exist at all times masters can operate as master-transmitters or as
master-receivers.
• The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data
corruption if two or more masters simultaneously initiate data transfer systems.
• Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard
mode or up to 400 KBit/s in the fast mode.
Platform: |
Size: 788480 |
Author: lu |
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Description: spi slave 8bit address 1bit r/w 7bit number data
Platform: |
Size: 155648 |
Author: im |
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Description: 24bit，SPI接口ADC，单电源供电3V或者5V，可编程输入范围(+ -2.56 V or + -160 mV)-FEATURES
2-Channel, 24-Bit - ADC
Pin Configurable (No Programmable Registers)
Pin Selectable Input Channels
Pin Programmable Input Ranges (2.56 V or 160 mV)
Fixed 19.79 Hz Update Rate
Simultaneous 50 Hz and 60 Hz Rejection
24-Bit No Missing Codes
18.5-Bit p-p Resolution (2.56 V Range)
16.5-Bit p-p Resolution (160 mV Range)
INTERFACE
Master or Slave Mode of Operation
Slave Mode
3-Wire Serial
SPI™ , QSPI™ , MICROWIRE™ , and DSP-Compatible
Schmitt Trigger on SCLK
POWER
Specified for Single 3 V and 5 V Operation
Normal: 1.3 mA @ 3 V
Power-Down: 9 A
ON-CHIP FUNCTIONS
Rail-Rail Input Buffer and PGA
APPLICATIONS
Sensor Measurement
Industrial Process Control
Temperature Measurement
Pressure Measurements
Weigh Scales
Portable Instrumentation
Platform: |
Size: 108544 |
Author: 张永辉 |
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Description: 使用AVR单片机模拟成DS2450的bascomAVR程序，实现了模拟1wire从机的功能。程序使用bascom语言编写，程序构建简单明了，对使用其它语言编写模拟1wire程序也具有参考的作用-Simulated using the AVR microcontroller into the DS2450' s bascomAVR procedures to achieve a simulation 1wire slave function. Bascom language program uses the program to build simple and clear, the use of other languages analog 1wire program also has the role of reference
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Size: 336896 |
Author: 李璇 |
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Description: The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.-The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.
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Size: 478208 |
Author: wei |
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Description: This document describes the MODBUS over Serial Line protocol. MODBUS Serial Line protocol is a Master-Slave protocol. This
protocol takes place at level 2 of the OSI model.
A master-slave type system has one node (the master node) that issues explicit commands to one of the "slave" nodes and processes
responses. Slave nodes will not typically transmit data without a request from the master node, and do not communicate with other
slaves.
At the physical level, MODBUS over Serial Line systems may use different physical interfaces (RS485, RS232). TIA/EIA-485 (RS485)
Two-Wire interface is the most common. As an add-on option, RS485 Four-Wire interface may also be implemented. A TIA/EIA-232-
E (RS232) serial interface may also be used as an interface, when only short point to point communication is required. (see chapter
"Physical Layer")
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Size: 229376 |
Author: RAMAKERS_R |
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Description: msp430f149 spi通信,用户可以通过SPI的发送和接受中断标志位来完成协议的控制。-msp430f149 spi,MSP-FET430P140 Demo- USART0, SPI Full-Duplex 3-Wire Slave P1.x Exchange
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Size: 312320 |
Author: fewei |
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Description: // Serial Peripheral Interface (SPI)
// The VSPI core implements an SPI interface compatible with the many
// serial EEPROMs, and microcontrollers. The VSPI core is typically used
// as an SPI master, but it can be configured as an SPI slave as well.
//
-// Serial Peripheral Interface (SPI)
//
// The VSPI core implements an SPI interface compatible with the many
// serial EEPROMs, and microcontrollers. The VSPI core is typically used
// as an SPI master, but it can be configured as an SPI slave as well.
//
// The SPI bus is a 3 wire bus that in effect links a serial shift
// register between the "master" and the "slave". Typically both the
// master and slave have an 8 bit shift register so the combined
// register is 16 bits. When an SPI transfer takes place, the master and
// slave shift their shift registers 8 bits and thus exchange their 8
// bit register values.
//
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Size: 7168 |
Author: william |
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Description: 3-wire interface slave
tape out verification ok
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Size: 1024 |
Author: 林文榮 |
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Description: VHDL 语言实现的串转并 SPI 等等
实现-The SPI bus is a 3 wire bus that in effect links a serial shift-- register between the master and the slave . Typically both the-- master and slave have an 8 bit shift register so the combined-- register is 16 bits. When an SPI transfer takes place, the master and-- slave shift their shift registers 8 bits and thus exchange their 8-- bit register values.
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Size: 1024 |
Author: 向东 |
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Description: 通过 Modbus 通讯 RS485 型物理链路，或装有适当变换器的其他接口使 Sepam 能
与远程监控系统连接。
Sepam 采用的 Modbus 规约与 RTU Modbus (1) 规约的子集兼容 ( 一个 Modbus 主
机可以同多个 Sepam 单元通讯 )。 Sepam 永远是子机 ( 从站 )。
所有 Sepam 单元均可配置 ACE949-2 ( 二线 ) 或 ACE959 ( 四线 ) 接口与通讯网络
连接。
RS485 和 ACE937 可连接到通讯网络，光纤通讯星形系统。-Communication via Modbus RS485 type physical link, or fitted with suitable converters other interfaces can make Sepam
Connection with a remote monitoring system.
Sepam uses a subset of the Modbus protocol with RTU Modbus (1) of the Statute compatible (a Modbus master
Machine unit can communicate with a plurality of Sepam). Sepam is always a slave (slave).
All Sepam unit can be configured ACE949-2 (wire) or ACE959 (four-wire) communications network interface
connection.
RS485 and ACE937 can be connected to the communications network, fiber-optic communication star system.
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Size: 1092608 |
Author: 万泽洪 |
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Description: This archive contain project for Atmel Studio v6.2 with target processor Atmega328P( used on the Arduino Nano board). Inside project you can find port for real-time operational sistem ChibioOS/RT v 3.0.3. Also implemented modbus RTU slave and 1-wire bus master for onewire device like DS18B20.
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Size: 1397760 |
Author: Greeds74
|
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Description: The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7, and UART8).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability.
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Size: 11092992 |
Author: charmee
|
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Description: CH374是一个USB总线的通用接口芯片，支持USB-HOST主机方式和USB-DEVICE/SLAVE设备方式，内置3端口HUB根集线器，支持低速和全速的控制传输、批量传输、中断传输以及同步/等时传输。在本地端，CH374具有8位数据总线和读、写、片选控制线以及中断输出，可以方便地挂接到单片机/DSP/MCU/MPU等控制器的系统总线上。除此之外，CH374还提供了节约I/O引脚的SPI串行通讯方式，通过3线或者4线SPI串行接口以及中断输出与单片机/DSP/MCU/MPU等相连接。(CH374 is a universal interface chip for USB bus, supports USB-HOST host mode and USB-DEVICE / SLAVE device mode, built-in 3-port HUB root hub, supports low-speed and full-speed control transmission, batch transmission, interrupt transmission, and synchronization / isochronous transmission. At the local end, CH374 has an 8-bit data bus and read, write, chip select control lines, and interrupt output, which can be easily connected to the system bus of a microcontroller / DSP / MCU / MPU controller. In addition, CH374 also provides a SPI serial communication method that saves I / O pins. It is connected to a single-chip computer / DSP / MCU / MPU through a 3- or 4-wire SPI serial interface and interrupt output.)
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Size: 3163136 |
Author: 17273423 |
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