Search - memory vhdl

Search - memory vhdl - List

[Other resource] vhdl程序例子 DL : 0: vhdl程序源代码，包括Combinational Logic Counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic等-VHDL source code, including Combinational Logic Counters Shift Registers State Machines Registers Memory Systems ADC and DAC Arithmetic etc.
Date : 2008-10-13 Size : 165.45kb User : 王力
[Other resource] EvsStore DL : 0: 用VHDL编写的由FPGA控制SDRAM的存储控制程序-VHDL prepared by the FPGA control SDRAM memory control procedures
Date : 2008-10-13 Size : 924byte User : 杨承凯
[Other resource] my_ramlib_06 DL : 0: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Date : 2008-10-13 Size : 601.62kb User : ruan
[Other resource] VHDL_Memory_Library_Code DL : 0: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Date : 2008-10-13 Size : 23.17kb User : Jawen
[Other resource] byvhdstopwatchl DL : 0: 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design)
Date : 2008-10-13 Size : 1.95kb User : 方周
[Other resource] VHDL.fifo DL : 0: 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
Date : 2008-10-13 Size : 1.12mb User : 黎莉
[Other resource] S3Demo DL : 0: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Date : 2008-10-13 Size : 714.42kb User : Roy Hsu
[Other resource] cf_vhdl DL : 0: CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.
Date : 2008-10-13 Size : 684.2kb User : gbh
[Other resource] MyCPU16 DL : 0: 16位cpu设计VHDL源码，其中包括alu，clock，memory等部分的设计
Date : 2008-10-13 Size : 1.04mb User : 孙冰