Search - VHDL fifo

Search - VHDL fifo - List

[Other] HowtosimulateIPCore DL : 0: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Date : 2026-01-02 Size : 351kb User : 任学
[Other] VHDL_PS2 DL : 0: 详细说明:基于VHDL 语言的 PS2 接口协议键盘驱动,VHDL 实现,PS2键盘的接收部分(主机一般很少向键盘发送数据),带FIFO 的。-Description: Based on the VHDL language interface protocol PS2 keyboard driver, VHDL implementation, the receiving part (the host to send data to the keyboard rarely) PS2 keyboard with FIFO.
Date : 2026-01-02 Size : 299kb User : 吴家