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[Program doc] fftIPCore的使用文档（中文） DL : 1: Date : 2009-11-03 Size : 1.25mb User : iteagle
[Program doc] FullParallelFFTBasedonFPGA DL : 0: 一种基于FPGA 实现的全并行结构FFT 设计方法，采用全并行加流水结构, 可在一个时钟节拍内完成32 点FFT 运算的功能, 设计最高运算速度可达11ns-FPGA-based parallel architecture to achieve the full FFT design methodology, the use of the entire parallel increase in water structure, in a beat the clock to complete 32-point FFT computation function, the design maximum speed of up to 11ns
Date : 2025-12-31 Size : 400kb User : wudi
[Program doc] a_sistolic_FFT_architecture_for_FPGA DL : 0: Description of a sistolic arhictecture for a FFT implementation in FPGA.
Date : 2025-12-31 Size : 165kb User : rhadookoo
[Program doc] FPGAFFT DL : 0: 用FPGA实现FFT的算法分析,硬件介绍!-FFT with FPGA realization of the algorithm analysis, hardware introduced!
Date : 2025-12-31 Size : 35kb User : 任杏
[Program doc] d DL : 0: IP核应用，详细的介绍了关于FPGA中IP核的应用-IP core application, a detailed presentation on the application of FPGA in the IP core ,,,,,,
Date : 2025-12-31 Size : 689kb User : 洪依
[Program doc] latch DL : 0: Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made between of kcm and multiplier. The implementation results show a significant improvement in performance in terms of area, power & timing. In This paper, we propose to design an 8-point FFT using kcm instead of complex multiplier and multiplier. Here our goal is to implement Radix-2 8-point FFT in hardware using hardware language (verilog) here time constraint is measured with the help of Xilinx FPGA (Field Programmable Gate Array).
Date : 2025-12-31 Size : 547kb User : Bahu