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现代先进微处理器有非常高的集成度和复杂度,又有寄存器堆、Cache等嵌入式部件,而且芯片管脚数相对较少,必须要有一定的自测试设计和其它的可测试性设计来简化测试代码,提高故障覆盖率。本文简要讨论NRS4000微处理器芯片的以边界扫描测试为主体,以自测试为补充的可测试性设计框架。着重介绍芯片的边界扫描设计和芯片中译码控制器PLA和微程序ROM以及采用内嵌RAM结构的指令Cache和寄存器堆的内建自测试设计。仿真结果表明,这些可测试性设计大大缩短了测试代码的长度。-modern microprocessors have a very high degree of integration and complexity, there Register pile, Cache such as embedded components, but Chip few relatively small, There must be the self-test design and testing of other design code to simplify testing, fault coverage. This paper briefly discussed Key words microprocessor chip to the boundary-scan test as the mainstay, Since the test to add to the test design framework. Highlighting the boundary-scan chip design and chip decoder PLA and micro-controller procedures and the use of embedded ROM RA M structure of the instruction cache and register stack of built-in self-test design. The simulation results show that these tests can greatly shorten the design of the test code length.
Date : 2025-12-25 Size : 40kb User : chengp

LDPC decoder thesis with development details
Date : 2025-12-25 Size : 2.76mb User : Sam

Development of LDPC Encoder/Decoder core
Date : 2025-12-25 Size : 254kb User : Sam

Reed Solomon Decoder: TMS320C64x Implementation
Date : 2025-12-25 Size : 307kb User : daniel

Power consumption of Reed-Solomon decoder algorithms.
Date : 2025-12-25 Size : 177kb User : tn

DESIGN AND IMPLEMENTATION OF A MULTITHREADED HIGH RESOLUTION MPEG4 DECODER ON SANDBLASTER DSP
Date : 2025-12-25 Size : 99kb User : xuweijing

Radio freuency transmitter and receiver
Date : 2025-12-25 Size : 78kb User : swapnil

RS编码英文论文Reed-Solomon Decoder Hardware Implemented in FPGAs: A Prospectus -Reed-Solomon Decoder Hardware Implemented in FPGAs: A Prospectus
Date : 2025-12-25 Size : 69kb User : 陈晨

The manuscript describes performance comparison of nearest-neighbor interpolation and bilinear to reduce the complexity of decoder WZVC.
Date : 2025-12-25 Size : 196kb User : imow

本文重点研究了高速8b/10b解码器的设计与实现,在详细介绍了解码原理及 多种传统解码方案的基础上,采用流水线结构设计了高速8b/10b解码器。通过 仔细分析传统解码器的不足,精心设计流水线结构及触发器在关键路径上的插入 点,使得所设计电路的速度比传统解码器有了较大的提升。-This paper focuses on the 8b/l 0b decoder,including the decoding principles and a variety of decoding schemes which will be analyzed and compared in this paper. With careful analysis of conventional decoder,pipelined decoder is well designed and insertion points on the critical path are carefully selected.
Date : 2025-12-25 Size : 9.5mb User : 梧桐雨
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