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[Software Engineering] FPGAandSDRAM DL : 0: 基于FPGA技术的存储器设计及其应用原理详细！！！1-Memory-based FPGA technology design and application of the principle of detail! ! ! 1
Date : 2026-01-09 Size : 4kb User : JP
[Software Engineering] SDRAMController DL : 0: SDRAM Controller 设计详细文档，很有参考价值！-SDRAM Controller Design of detailed documentation, a good reference!
Date : 2026-01-09 Size : 436kb User : 王一
[Software Engineering] median DL : 0: 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1, b1, c1)
Date : 2026-01-09 Size : 2kb User : 刘文英
[Software Engineering] TheResearchoftherealtimesignalprocessingofSARbased DL : 0: 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配，满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA 的实现方法及仿真结果。-he FPGA s development and debugging are implemented,including FFT, IFFT, CMUL and C0ntrol of CTM．Based Oll this，Implementation of a high efficient corner turn memory arithmetic with writing and reading by row based on DDR SDRAM is introduced．When using CTM with this algorithm，me speed of reading and writing maItches and meets the requirement of pipelined operation．Finally a method of model implementation for complex image based on CORDIC algorithm is introduced．The algorithm’s hardware implementation structure is analysed, and implementation methodology and simulation results are given
Date : 2026-01-09 Size : 4.92mb User : mabeibei
[Software Engineering] SDRAM DL : 0: 连接Nios II 和SDRAM的系统设计，DDR SDRAM设计及调试经验总结，MT48LC16M16资料。-failed to translate
Date : 2026-01-09 Size : 1.82mb User : luyi
[Software Engineering] 040402~~ DL : 0: 虽然与SRAM相比，SDRAM需要额外的控制逻辑，有更复杂的时序要求，需要定时刷新，但是由于SDRAM具有单位空间存储容量大和价钱便宜的优点，因而被许多的嵌入式开发者所青睐。为此，针对这种情况，必须设计SDRAM控制器。为了降低系统成本，本课题采用FPGA技术，并使用VHDL语言研究了FPGA与SDRAM的存储器接口实现问题。-Abstract In order to expand the SDRAM’S storage capacity of the TS一101 processor，a method is pro— posed for implementing the SDRAM controller based on FPGA．The characteristics of the corresponding SDRAM are analyzed and the schematic diagrams and the timing are given．The function of modules and per- formance of SDRAM storage board are described．The design method of modularization is adopted in FPGA． This design expands the SDRAM’S storage capacity of the TS-101 processor to 512Mbytes．
Date : 2026-01-09 Size : 249kb User : zhangying
[Software Engineering] ddr_sdr_V1_1 DL : 0: its the vhdl stuff for ddr sdram controller nice one easily understandable-its the vhdl stuff for ddr sdram controller nice one easily understandable
Date : 2026-01-09 Size : 37kb User : james
[Software Engineering] DDRSDRAM DL : 0: 基于VHDL的DDR SDRAM控制器的设计，实现数据的读写功能，迸发长度分为2，4，8-Based on the VHDL DDR SDRAM controller design, implementation of data read and write capabilities, burst into the length of 2, 4, 8
Date : 2026-01-09 Size : 804kb User : zhangjiefei