Search - switch VHDL

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[Software Engineering] DigitalssStopwatch DL : 0: 本秒表计时器用于体育竞赛及各种要求有较精确时的各领域。此计时器是用一块专用的芯片，用VHDL语言描述的。它除开关、时钟和显示功能以外，它还包括1/100s计时器所有的控制和定时功能，其体积小，携带方便。-the stopwatch timer for the various sports competitions and requires more accurate at the various fields. This timer is a dedicated chip, using the VHDL description. In addition to its switch, the clock and display functions, but also include 1 / 100 seconds timer control and all the regular functions, its small size and easy to carry.
Date : 2008-10-13 Size : 6.79kb User : 段苛苛
[Software Engineering] DigitalssStopwatch DL : 0: 本秒表计时器用于体育竞赛及各种要求有较精确时的各领域。此计时器是用一块专用的芯片，用VHDL语言描述的。它除开关、时钟和显示功能以外，它还包括1/100s计时器所有的控制和定时功能，其体积小，携带方便。-the stopwatch timer for the various sports competitions and requires more accurate at the various fields. This timer is a dedicated chip, using the VHDL description. In addition to its switch, the clock and display functions, but also include 1/100 seconds timer control and all the regular functions, its small size and easy to carry.
Date : 2025-12-30 Size : 7kb User : 段苛苛
[Software Engineering] vhdl DL : 0: library ieee use ieee.std_logic_1164.all entity decoder is port (clk:in std_logic clr:in std_logic data_in:in std_logic --待解码信元输入端； data_out:out std_logic) --解码信元输出端； end decoder architecture behave of decoder is component dff2 --上升沿D 触发器； port(d,clk,clr:in std_logic q:out std_logic) end component component xor2 --两输入异或门； port (a,b:in std_logic y:out std_logic) end component --一输入两输出电子开关； component switch21 port (clk,d,clr:in std_logic y:out std_logic) end component component emendation --校正电路； port (d,clk,clr:in std_logic y:out std_logic) end component signal s1,s2,s3,s4,s5: std_logic begin u0:switch21 port map (data_in ,clk,clr,s1,s2) u1: emendation port map (s1,clk,clr,s3) u2: dff2 port map (s2,clk,clr,s4) u3: xor2 port map (s3,s4,s5) data_out <= s5 end -library ieee use ieee.std_logic_1164.all entity decoder is port (clk: in std_logic clr: in std_logic data_in: in std_logic - be decoded cell inputs data_out: out std_logic) - Decoding Cell output end decoder architecture behave of decoder is component dff2- edge D flip-flop port (d, clk, clr: in std_logic q: out std_logic) end component component xor2- two input XOR gate port (a, b: in std_logic y: out std_logic) end component - an input two output electronic switch component switch21 port (clk, d, clr: in std_logic y: out std_logic) end component component emendation- correction circuit port (d, clk, clr: in std_logic y: out std_logic) end component signal s1, s2, s3, s4, s5: std_logic begin u0: switch21 port map (data_in, clk , clr, s1, s2) u1: emendation port map (s1, clk, clr, s3) u2: dff2 port map (s2, clk, clr, s4) u3: xor2 port map (s3, s4, s5) data_out < = s5 end
Date : 2025-12-30 Size : 369kb User : 刘轩赫