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电子科大2009-数字中频技术的研究与FPGA实现,主要是DDC的FPGA实现,NCO部分的FPGA实现!-UESTC 2009- Digital IF Research and FPGA, the FPGA implementation is mainly DDC, NCO segment FPGA to achieve!
Date : 2026-01-10 Size : 5.58mb User : peter

要求设计一个带闹钟功能的24小时计时器 它包括以下几个组成部分: ① 显示屏:4个七段数码管显示当前时间(时:分)或设置的闹钟时间;一个发光二极管以1HZ的频率跳动,用于显示秒; ② 按键key1,用于设置调时还是调分; ③ 按键key2,用于输入新的时间或新的闹钟时间,每按下一次,时或分加1; ④ TIME(时间)键,用于确定新的时间设置; ⑤ ALARM(闹钟)键,用于确定新的闹钟时间设置,或显示已设置的闹钟时间; ⑥ 扬声器,在当前时钟时间与闹钟时间相同时,发出蜂鸣声。 -To design a 24-hour alarm clock with a timer which includes the following components: ① Display: 4 segment digital tube displays the current time (hours: minutes) or set the alarm time a light-emitting diode to the frequency of 1HZ beating, is used to display seconds ② keys key1, when used to set the tone or the tone pm ③ key key2, used to enter the new time or a new alarm time, every time you press, or points plus 1 ④ TIME ( time) key, used to determine the new time settings ⑤ ALARM (alarm) button, used to determine a new set alarm time, or set the alarm time is displayed ⑥ Speaker, in the current time and alarm clock the same time, issue beep.
Date : 2026-01-10 Size : 253kb User : 洪巨成

vhdl 七段数码管代码 可以把代码转换成可以在七段数码管上显示的代码-Seven-Segment LED vhdl code into the code can be displayed in seven sections of the code on the digital
Date : 2026-01-10 Size : 4kb User : zhaohong

vhdl语言编写的7段数码管译码器,包含了全部代码和工程图-7-segment LED decoder vhdl language contains all the code and drawing
Date : 2026-01-10 Size : 163kb User : 张瑞萌

it shows 4-bit full adder with 7-segment and you can start vhdl with this code
Date : 2026-01-10 Size : 206kb User : mhj

It s a sept segment display VHDL simulation
Date : 2026-01-10 Size : 301kb User : master

GAME.vhdl, VGA.vhdl VGA module.vhdl seven segment.vhdl
Date : 2026-01-10 Size : 11.69mb User : Muzaffer
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