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[Software Engineering] FPGAandSDRAM DL : 0: 基于FPGA技术的存储器设计及其应用原理详细！！！1-Memory-based FPGA technology design and application of the principle of detail! ! ! 1
Date : 2026-01-03 Size : 4kb User : JP
[Software Engineering] FPGA_4FFT DL : 0: 针对高速数字信号处理的要求,提出用FPGA 实现基- 4FFT 算法,并对其整体结构、蝶形单元进行了分析. 采用蝶算单元输入并行结构和同址运算,能同时提供蝶形运算所需的4 个操作数,具有最大的数据并行性,能提高处理速度按照旋转因子存放规则,蝶形运算所需的3 个旋转因子地址相同,且寻址方式简单输出采取与输入相似的存储器运算单元同时采用3 个乘法的复数运算算法来实现.-In accordance with the requirements of high speed digital signal processing , the algorithmof radix O4 implemented with FPGA and the integrated architecture and butterfly unit are analyzed. With butterfly u2 nit input which is designed by parallel structure and the same address calculation , four operation codes the butterfly unit needs can be provided simultaneously to have the most data parallel and improve the speed of calculation. According to the rotation parameters memory regulation , the addresses of three rotation parame2 ters of butterfly unit are the same with simple style of address generation and similar input and output memo2 ries. The operating unit adopted is implemented by three complex calculation algorithm of multiplication si2 multaneously.
Date : 2026-01-03 Size : 352kb User : 王晓
[Software Engineering] CRC DL : 0: 　本文提出一种通用的CRC 并行计算原理及实现方法,适于不同的CRC 生成多项式和不同并行度(如8 位、16 位、及32 位等) ,与目前已采用的查表法比较,不需要存放余数表的高速存储器,减少了时延,且可通过增加并行度来降低高速数传系统的CRC 运算时钟频率.-In this paper, a universal principle of CRC and implementation of parallel computing methods for generating different CRC polynomial and different degree of parallelism (eg, 8, 16, and 32-bit, etc.), with the current look-up table method has been used in comparison do not store more than a few tables, high-speed memory, reducing latency, and degree of parallelism can be increased to reduce the high-speed data-transmission system clock frequency of the CRC computation.
Date : 2026-01-03 Size : 141kb User : 黑月
[Software Engineering] dso DL : 0: 使用VHDL语言编写的简易数字存储示波器，用MAX+PlusII仿真验证。VHDL编写了采样、存储写、存储读和显示4个模块。采样使用ADC0809，存储器使用6264，显示使用DAC0832。-The design of the chip as a high-speed signal ADC0809 the A/D converter, SRAM6264 memory for data storage after sampling, DAC0832 chip as a signal of D/A conversion. Programming using ultra-high-speed hardware description language VHDL description of its A/D conversion, A/D sampling controller and data storage, digital output programming, simulation, the completion of the design of hardware and software, as well as some of the experimental prototype debugging
Date : 2026-01-03 Size : 491kb User : 兰江营
[Software Engineering] spartan6_fpga_blockram_user_guide DL : 0: Spartan6　FPGA中的块存储器使用指南，可以构建为FIFO，ROM，RAM，移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
Date : 2026-01-03 Size : 368kb User : james
[Software Engineering] fifo_template DL : 0: aes code with fifo control to memory
Date : 2026-01-03 Size : 9kb User : allen
[Software Engineering] OneNAND_in_embed_sys DL : 0: OneNAND闪存在嵌入式系统中的应用 OneNAND Flash是三星公司开发的一类Flash芯片，它克服了传统NAND Flash接口复杂的缺点，具有接口简单、读写速度快、容量大、寿命长、成本低等优点。文章从软硬件两方面介绍了其在嵌入式系统中的应用，特别是逻辑块和物理块地址的映射、读写擦操作、坏块处理、性能优化等技术。-OneNAND flash memory in embedded system applications developed by Samsung' s OneNAND Flash is a type Flash chips, which overcomes the traditional shortcomings of NAND Flash interface, a complex with a simple interface, read and write speed, large capacity and long life and low cost advantages. The article describes both hardware and software in embedded system applications, in particular logical block and physical block address mapping, read and write wiping operation, bad block handling, performance optimization technologies.
Date : 2026-01-03 Size : 47kb User : zhangdong
[Software Engineering] TheResearchoftherealtimesignalprocessingofSARbased DL : 0: 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配，满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA 的实现方法及仿真结果。-he FPGA s development and debugging are implemented,including FFT, IFFT, CMUL and C0ntrol of CTM．Based Oll this，Implementation of a high efficient corner turn memory arithmetic with writing and reading by row based on DDR SDRAM is introduced．When using CTM with this algorithm，me speed of reading and writing maItches and meets the requirement of pipelined operation．Finally a method of model implementation for complex image based on CORDIC algorithm is introduced．The algorithm’s hardware implementation structure is analysed, and implementation methodology and simulation results are given
Date : 2026-01-03 Size : 4.92mb User : mabeibei
[Software Engineering] source_code DL : 0: verilog code fifo memory usb
Date : 2026-01-03 Size : 4kb User : mohsen
[Software Engineering] RAMinVHDL DL : 0: How to create a RAM memory in VHDL
Date : 2026-01-03 Size : 323kb User : jose