Search - accumulator

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[Software Engineering] PREDICTION.FRACTIONALN.SPURS DL : 0: Fast settling-time added to the already conflicting requirements of narrow channel spacing and low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete \"beat-note spurious levels from arbitrary modulus divide sequences including those from classic accumulator methods.
Date : 2008-10-13 Size : 408.52kb User : 谢振
[Software Engineering] PREDICTION.FRACTIONALN.SPURS DL : 0: Fast settling-time added to the already conflicting requirements of narrow channel spacing and low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete "beat-note spurious levels from arbitrary modulus divide sequences including those from classic accumulator methods.
Date : 2025-12-14 Size : 408kb User : 谢振
[Software Engineering] 555 DL : 0: 按照要求设计指令系统，该指令系统能够实现数据传送，进行加、减运算和无条件转移，具有累加器寻址、寄存器寻址、寄存器间接寻址、存储器直接寻址、立即数寻址等五种寻址方式-In accordance with the requirements of the design of instruction, the instruction set to achieve data transmission, for add, subtract operation and unconditional transfer, with accumulator addressing, register addressing, register indirect addressing, memory direct addressing, immediate addressing, such as the number five addressing mode
Date : 2025-12-14 Size : 232kb User : twh
[Software Engineering] JSJ DL : 0: 2.1 设计总要求 2.1.1 实验计算机的外设需求该实验计算机具有键盘和打印机两种外部设备。外设和内存统一操作指令，程序查询法使用外设。 2.1.2实验计算机运算器结构运算器采用单累加器多通用寄存器结构 2.1.3实验计算机功能和用途能执行键盘输入的奇数i (i=1-255)回打出来并存入100H号开始的内存单元中。 -2.1 Design of the general requirements of 2.1.1 Experimental computer peripheral needs of the experiment the computer keyboard and printer with two types of external equipment. Peripherals and memory to operate a unified command, the program queries the use of peripherals law. 2.1.2 Experimental computing architecture computing device using a single accumulator register more generic structure 2.1.3 Experimental computer functions and uses keyboard input to the implementation of the odd-numbered i (i = 1-255) and deposited back to playing out of memory starting 100H unit.
Date : 2025-12-14 Size : 80kb User : 方方
[Software Engineering] plugin-tut_timing_verilog_Lab2 DL : 0: manual for time analysis and testing the critical path in verilog FPGA using Accumulator design
Date : 2025-12-14 Size : 380kb User : ahmed
[Software Engineering] DDS1 DL : 0: 直接数字频率合成器（Direct Digital synthesizer）是从相位概念出发直接合成所需波形的一种频率合成技术。一个直接数字频率合成器由相位累加器、加法器、波形存储ROM、D/A转换器和低通滤波器（LPF）构成-Direct digital frequency synthesizer (Direct Digital synthesizer) is the concept of direct synthesis from the requirements phase of a waveform synthesizer technology. A direct digital frequency synthesizer by the phase accumulator, adder, waveform storage ROM, D/A converter and low pass filter (LPF) constitute
Date : 2025-12-14 Size : 255kb User : wufeng
[Software Engineering] 222 DL : 0: pipelined multiplier accumulator architecture
Date : 2025-12-14 Size : 308kb User : Karama
[Software Engineering] jia DL : 0: 摘要:介绍了利用直接数字合成技术产生频率扫描信号的新方法。利用计数器和相位累加器实现对波形存储器寻址, 从而产生频率扫描信号序列。该序列通过数-模转换器和低通滤波器后, 产生出频率扫描信号。被合成的频率扫描信号的起始频率、终止频率和扫描时间可根据需要随意设定,并且可以实现对三者的精确控制。-Abstract: The use of direct digital synthesis techniques to create a new method of frequency sweep signal. The use of counters and phase accumulator to achieve the waveform memory addressing, resulting in a frequency sweep signal sequence. The sequence through the number- analog converter and low pass filter, to produce a frequency sweep signal. Was synthesized frequency sweep signal the start frequency, stop frequency and sweep time can be arbitrarily set according to need, and can achieve precise control of the three.
Date : 2025-12-14 Size : 145kb User : 贾琼
[Software Engineering] 01-(3) DL : 0: 基于单片机8031的太阳能交通警示牌的设计，以太阳能为能源, 给蓄电池加上充、放电保护装置, 防止过充电和过放电。该警示板设置在夜间有事故隐患的路段, 以太阳能光伏板为传感器的光控电路, 控制LED 在白天关闭、夜间开启。-This design takes the solar energy as the energy, adds on the electric discharge protective device sufficiently to the accumulator cell, prevents the surcharge and the electric discharge. This police shows the board to establish has the accident hidden danger road section in at night, by photovoltaic board the sensor light controls the electric circuit, controls LED to close, at night, in the daytime to open
Date : 2025-12-14 Size : 344kb User : 杨玮
[Software Engineering] architecture-course-design DL : 0: 组成原理课程设计编写应用程序，实现以下功能：通过机器指令集实现两个二进制数的四则运算。数据通过IN指令输入到A累加器中，输入菜单选项选取运算的方式（1：乘法，2：加法，3：减法，4：除法）。输入形式：数据输入形式为二进制，第一个数据为第一个运算数，第二个数据为第二个运算数，第三个数据为菜单选项。输出形式：通过实验箱上的out输出端口显示，显示形式为十六进制数。实现说明：乘法：通过循环使用加法实现乘法功能，第二个操作数作为被乘数，对其自身累加，当累加等于第一个操作数的时候，记录其累加次数，此累加次数便是out输出的结果。加法：通过现有指令ADD实现两个操作数的加法运算减法：通过现有指令SUB实现两个操作数的减法运算除法：通过循环使用ADD，SUB指令和JC，JZ比较运算数的大小实现除法功能，将除数作为倍数累加，不断与被除数比较大小最后得出最终的累计次数，得出计算结果。-Architecture course design Write applications to achieve the following functions: Two binary number four machine instruction set computing. Data IN instruction input to the A accumulator input menu option selected operator (1: multiplication, 2: Addition 3: subtraction, 4: division). Input forms: the form of input data to binary, the first data for the first operand, the second data for the second operand, the third data as a menu option. Output in the form: out output port on the test box is displayed, showing the form of a hexadecimal number. Implementation Notes: Multiplication: cycle through the use of addition and multiplication function, the second operand as a multiplicand, accumulation of its own, when the accumulation is equal to the first operand, recording its accumulated number of times, the accumulated number of times is the result of the out output . Addition: the addition of the two operands through existing instruction ADD Subtraction: the su
Date : 2025-12-14 Size : 3.01mb User : xyy
[Software Engineering] driver_v3.2 DL : 0: Led driver for lipo accumulator with firmware C++ source
Date : 2025-12-14 Size : 28kb User : mikrotik
[Software Engineering] fpmac-90nm DL : 0: A pipe-lined single-precision floating-point multiply accumulator, operations at speeds exceeding 3 GHz with single-cycle throughput, achieves 6.2 G Flops of performance while dissipating 1.2 W at 3.1 GHz, 1.3-V supply.-A pipe-lined single-precision floating-point multiply accumulator, operations at speeds exceeding 3 GHz with single-cycle throughput, achieves 6.2 G Flops of performance while dissipating 1.2 W at 3.1 GHz, 1.3-V supply.
Date : 2025-12-14 Size : 2.04mb User : Sreeram Kalangiri