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[OS Develop] WYOS0.00b DL : 0: 我自己写的一个实模式的操作系统，支持fat12文件系统和一个和shell整合到一起的简单的键盘驱动，目前正在实现pci总线驱动程序。以后将会转入到保护模式下开发-I wrote it myself a real mode of the operating system, support FAT12 file system and a shell and the integration with a simple keyboard-driven, are currently achieving pci bus driver. After that it will enter a protected mode development
Date : 2008-10-13 Size : 122.44kb User : 刘硕
[OS Develop] Chauffeur_Conductor DL : 0: 本代码实现了操作系统中的司机和售票员同步问题，应用了VC中的信号灯，是我学完P、V操作后写的，希望于大家分享。-the code of the operating system and the driver and conductor of the bus synchronization, application of the VC's appearance, I studied End P, V written after the operation, which we hope to share with you all.
Date : 2008-10-13 Size : 11.74kb User : 陈锋
[OS Develop] CANdrv DL : 0: vxWorks下的can总线驱动，已经将can设备抽象为I/O设备，对can的访问可以像普通I/O一样操作-vxWorks the bus driver can have equipment can be abstracted as I / O equipment, on the visit can be like an ordinary I / O operation of the same
Date : 2008-10-13 Size : 10.46kb User : fellow
[OS Develop] can-0.7.1 DL : 0: can bus driver code.
Date : 2008-10-13 Size : 79.91kb User : fe
[OS Develop] cf_driverforLinux DL : 0: 基于ARM9200的CF卡驱动程序，按照9200处理器数据手册上的电路设计，采用直接IO方式访问CF卡，另外有通过PCMCIA总线方式连接CF卡，以后再上传-ARM9200 based on the CF card driver, According to 9200 data processor manual circuit design, the use of direct methods visit IO CF card, Another way through the PCMCIA bus connecting CF card, subsequent uploads
Date : 2008-10-13 Size : 4.11kb User : wangligang
[OS Develop] dpram DL : 0: Linux操作系统，PPC405EP处理器上的Local BUS和DPRAM双口RAM接口的驱动程序和详细说明，以及使用到的信号量通讯等的说明文档，是典型的中断加双口RAM通讯的例子，非常实用。
Date : 2008-10-13 Size : 280.04kb User : XueTao
[OS Develop] Chauffeur_Conductor DL : 0: 本代码实现了操作系统中的司机和售票员同步问题，应用了VC中的信号灯，是我学完P、V操作后写的，希望于大家分享。-the code of the operating system and the driver and conductor of the bus synchronization, application of the VC's appearance, I studied End P, V written after the operation, which we hope to share with you all.
Date : 2025-12-29 Size : 11kb User : 陈锋
[OS Develop] CANdrv DL : 0: vxWorks下的can总线驱动，已经将can设备抽象为I/O设备，对can的访问可以像普通I/O一样操作-vxWorks the bus driver can have equipment can be abstracted as I/O equipment, on the visit can be like an ordinary I/O operation of the same
Date : 2025-12-29 Size : 10kb User : fellow
[OS Develop] can-0.7.1 DL : 0: can bus driver code.
Date : 2025-12-29 Size : 80kb User : fe
[OS Develop] cf_driverforLinux DL : 0: 基于ARM9200的CF卡驱动程序，按照9200处理器数据手册上的电路设计，采用直接IO方式访问CF卡，另外有通过PCMCIA总线方式连接CF卡，以后再上传-ARM9200 based on the CF card driver, According to 9200 data processor manual circuit design, the use of direct methods visit IO CF card, Another way through the PCMCIA bus connecting CF card, subsequent uploads
Date : 2025-12-29 Size : 4kb User : wangligang
[OS Develop] dpram DL : 0: Linux操作系统，PPC405EP处理器上的Local BUS和DPRAM双口RAM接口的驱动程序和详细说明，以及使用到的信号量通讯等的说明文档，是典型的中断加双口RAM通讯的例子，非常实用。-Linux operating system, PPC405EP processor Local BUS and DPRAM Dual Port RAM interface drivers and a detailed description, and the use of semaphore communication documentation, etc., is a typical interruption plus dual-port RAM communication examples, very practical .
Date : 2025-12-29 Size : 280kb User : XueTao
[OS Develop] SPI DL : 0: SPI总线源代码。可以很好得学习SPI总线和SPI通信-SPI bus source code. Can be a very good learning SPI bus and SPI communication
Date : 2025-12-29 Size : 41kb User : andy
[OS Develop] PCI_DOS DL : 0: PCI总线在DOS操作系统下的驱动程序源代码-PCI bus in the DOS operating system driver source code
Date : 2025-12-29 Size : 79kb User : yyf
[OS Develop] program DL : 0: 设计实现4bit FIFO, 数据深度为8，产生满，空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the first data word written into the RAM is also the first data word retrieved from the RAM. As shown in the Figure 1, the RAM is implemented to operate as a FIFO. The RAM is assumed to have separate data inputs and outputs, an N-bit address bus (ADD) and an active high write enable (WE). The inputs to FIFO/Stack include PUSH, POP, INIT (all active high) in addition to the rising edge triggered CLK input. The FIFO logic will not only supply the address and write enable to the RAM, but will also supply active high flags for FULL, EMPTY, NOPOP, and NOPUSH conditions.
Date : 2025-12-29 Size : 3kb User : shao
[OS Develop] FIFO DL : 0: FIFO以及跨时钟域的同步问题。 FIFO有分离的地址总线和用以读写数据的数据通道，以及指示堆栈状态（满、将满等）的状态线。-FIFO as well as cross-clock domain synchronization. FIFO have separate address bus and read and write data to the data channel, as well as the instructions state stack (full, will be full, etc.) of the state line.
Date : 2025-12-29 Size : 3kb User : isaac
[OS Develop] CANv2.0 DL : 0: Can总线的技术协议以及应用介绍，希望对您有用。-Can bus technology agreements, as well as its application, and hope be useful for you.
Date : 2025-12-29 Size : 159kb User : 赵先生
[OS Develop] smi DL : 0: DOS PCI bus accessing library, written on C, uses DPMI
Date : 2025-12-29 Size : 28kb User : Vulg
[OS Develop] HMC5883-ceshichengxu DL : 1: 霍尼韦尔 HMC5883L 是一种表面贴装的高集成模块，并带有数字接口的弱磁传感器芯片，应用于低成本罗盘和磁场检测领域。HMC5883L 包括最先进的高分辨率HMC118X 系列磁阻传感器，并附带霍尼韦尔专利的集成电路包括放大器、自动消磁驱动器、偏差校准、能使罗盘精度控制在1°~2°的12 位模数转换器.简易的I2C 系列总线接口。HMC5883L 是采用无铅表面封装技术，带有16 引脚，尺寸为3.0X3.0X0.9mm。HMC5883L 的所应用领域有手机、笔记本电脑、消费类电子、汽车导航系统和个人导航系统。-Honeywell HMC5883L is a surface mount high integration module, and a digital interface for weak magnetic fieldThe sensor chip, applied to the low cost of compass and magnetic field detection. HMC5883L consists of the most advanced highResolution HMC118X series of magnetoresistive sensor, with Honeywell patented integrated circuit includes amplificationAutomatic degaussing device, drive, calibration, can make the compass precision control at 1degrees to 2 degrees12modulusConverter. Simple I2C serial bus interface. HMC5883L is the use of lead-free packaging technology, beltThere are16 pin, size 3.0X3.0X0.9mm. The application of HMC5883L field mobile phone, notebookComputer, consumer electronics, automotive navigation systems and personal navigation system.
Date : 2025-12-29 Size : 3kb User : 陈氏美
[OS Develop] IIC DL : 0: 实现一个i2c总线结构，采用verilog语言实现，主要用于总线结构的学习，大家可以看看！-A i2c bus architecture using verilog language, mainly used in the bus structure learning, we can see!
Date : 2025-12-29 Size : 2kb User : rsw
[OS Develop] bus DL : 0: 文件是一个用c++写的公交系统，供大家分享-The file is a written with c++, bus system, for all to share
Date : 2025-12-29 Size : 20kb User : susie

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