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[source in ebook] ADC DL : 0: stm32驱动4X4键盘扫描，用于键盘扫描-/******************************************************************************* * File Name : KeyScan * Description : Serial print out the corresponding key value *******************************************************************************/ #include"stm32f10x.h" #include"KeyScan.h" #include"SysTick.h" #include"USART.h" /******************************************************************************* * Function Name : main * Description : Main program. * Input : None * Output : None * Return : None *******************************************************************************/ int main(void) { SysTick_Init() //延时初始化 USART_GPIO_Config() //串口初始化 USART_Config() Keyboard_Interrupt_Init() //矩阵键盘初始化 while(1) { printf("\nBelieve yourself\n") delay_ms(1500) if(Keyboard_Val) { switch(Keyboard_Val) { case 1:printf("\n1\n") Keyboard_Val=0 break case 2:printf("\n2\n") Keyboar
Date : 2026-01-09 Size : 1kb User : henry
[source in ebook] dianzinengliangfenbu DL : 1: matlab编写的SF6/N2混合气体放电分析的程序，里面涉及蒙特卡洛法对混合气体的编写-SF6/N2 matlab prepared mixed gas discharge analysis procedure, which involves the Monte Carlo method for the preparation of the gas mixture
Date : 2026-01-09 Size : 3kb User : 王人
[source in ebook] dianzinengliangfenbu DL : 0: 蒙特卡洛法编写的N2气体放电分析，基于matlab程序编写-The monte carlo method to write N2 gas discharge analysis, based on the matlab programming
Date : 2026-01-09 Size : 3kb User : 王人
[source in ebook] majority DL : 0: modulemajority (major, V1, V2, V3) start your comments with a forward slash and star and finish it with a star and forward slash. output major inputV1, V2, V3 wireN1, N2, N3 and A0 (N1, V1, V2) andA1 (N2, V2, V3) and A2 (N3, V3, V1) orOr0(major, N1, N2, N3) // Use two forward slashes for one line comments Endmodule Each line of text in Verilog must terminate with a semicolon except endmodule. -modulemajority (major, V1, V2, V3) start your comments with a forward slash and star and finish it with a star and forward slash. output major inputV1, V2, V3 wireN1, N2, N3 and A0 (N1, V1, V2) andA1 (N2, V2, V3) and A2 (N3, V3, V1) orOr0(major, N1, N2, N3) // Use two forward slashes for one line comments Endmodule Each line of text in Verilog must terminate with a semicolon except endmodule.
Date : 2026-01-09 Size : 125kb User : nn