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[MPI] MY 80c51 IP DL : 0: verilog和vhdl混写的工程内含mc8051软核及最小系统经测试已调通(Verilog and VHDL mixed with the project, including the mc8051 soft core and the smallest system, the test has been transferred)
Date : 2025-12-24 Size : 16.15mb User : 嘿哟