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[assembly language] l7 DL : 0: 使用VHDL语言编写的简易数字存储示波器，用MAX+PlusII仿真验证。VHDL编写了采样、存储写、存储读和显示4个模块。采样使用ADC0809，存储器使用6264，显示使用DAC0832。-The design of the chip as a high-speed signal ADC0809 the A / D converter, SRAM6264 memory for data storage after sampling, DAC0832 chip as a signal of D / A conversion. Programming using ultra-high-speed hardware description language VHDL description of its A / D conversion, A / D sampling controller and data storage, digital output programming, simulation, the completion of the design of hardware and software, as well as some of the experimental prototype debugging -DAC0832。-The design of the chip as a high-speed signal ADC0809 the A/D converter, SRAM6264 memory for data storage after sampling, DAC0832 chip as a signal of D/A conversion. Programming using ultra-high-speed hardware description language VHDL description of its A/D conversion, A/D sampling controller and data storage, digital output programming, simulation, the completion of the design of hardware and software, as well as some of the experimental prototype debugging
Date : 2026-01-03 Size : 145kb User : 统一
[assembly language] CPUcoa-course-design DL : 0: 简单的cpu设计，包括memory，alu运算器，comp比较器以及控制器control，寄存器register等的vhdl编写的程序。-A simple cpu design, including memory, alu arithmetic logic unit, comp comparator and controller control, such as vhdl register register write programs.
Date : 2026-01-03 Size : 40.23mb User : 商客
[assembly language] SRAM DL : 0: 随机存储器（SRAM）的 vhdl 源代码-Static random access memory (SRAM) in vhdl source code
Date : 2026-01-03 Size : 337kb User : Liwag