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[Education soft system] iic DL : 0: IIC总线，把数据写入EEPROM，然后再读出并显示。-IIC bus, write the data into the EEPROM, and then read out and demonstrate.
Date : 2025-12-29 Size : 3kb User : hongabing
[Education soft system] zhinenggongjiaocheliangdepaiban DL : 0: 智能公交之车辆人员排班算法的研究与应用某大学研究生毕业论文-Intelligent Vehicles bus staff scheduling algorithm research and application of a university post-graduate thesis
Date : 2025-12-29 Size : 2.3mb User : terry
[Education soft system] CAN2BTutorial DL : 0: CAN2.0 B tutorial - Basic tutorial on CAN Bus 2.0B
Date : 2025-12-29 Size : 114kb User : Vijay
[Education soft system] DDS DL : 0: THIS SOFTWARE IS A MODIFIED, SIMPLIFIED AND COMMENTED VERSION OF A MORE COMPLICATED AND UN-COMMENTED VERSION OF SOFTWARE FOR THE CONTROL OF AD9951 FOUND ON: http://www.radioamatoriteamsviluppo.it (Thank to Author s). This version is made for the control of pre-mounted module KM.1644 of "Nuova Elettronica" whit only 3 pin : clock, data, update (and reset optionally) in SPI bus but through LPT 0378
Date : 2025-12-29 Size : 526kb User : pete68
[Education soft system] loadflow-with-matlab(30-bus-system) DL : 0: 30 BUS CODE ON MATLAB
Date : 2025-12-29 Size : 5kb User : bhavesh
[Education soft system] Lab3 DL : 0: 3 bus power system power flow analysis
Date : 2025-12-29 Size : 1kb User : ariel
[Education soft system] ReadWrite-RAM-VHDL-source-code DL : 0: This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus lines are 8 Hence, each location can store 8 bits (i.e. 1 byte each) ADR: in std_logc_vector (9 downto 0) D: inout std_logic_vector (7 downto 0) CS: in std_logic OE: in std_logic WR: in std_logic-This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus lines are 8 Hence, each location can store 8 bits (i.e. 1 byte each) ADR: in std_logc_vector (9 downto 0) D: inout std_logic_vector (7 downto 0) CS: in std_logic OE: in std_logic WR: in std_logic
Date : 2025-12-29 Size : 1kb User : ss
[Education soft system] Airline-Ticket-Reservation DL : 0: CONTRUCTING AN ARRAY FO BUS TICKETING PROGRAMME
Date : 2025-12-29 Size : 3kb User : kent
[Education soft system] IEEE_14_bus DL : 0: IEEE 14 bus system in PSCAD Software
Date : 2025-12-29 Size : 13kb User : Suhail
[Education soft system] Domain Specific Hardware Accelerators: Vector Processing Units DL : 0: This repository contains the source code for VLSI CAD Project, Domain Specific Hardware Accelerators, as apart of coursework in CS6230 : CAD for VLSI. Fall, 2020. What does this repo enclose? Overview The following components are implemented in Bluespec System Verilog: CPU RAM Bus Vector Processor CPU A minimal 2 stage pipelined inorder processor. Vector Processor A vector processor capable of: Vector Negation (int8, int16, int32, float32) Vector Minima (int8, int16, int32, float32)
Date : 2021-10-25 Size : 3.15mb User : nalevihtkas