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verilog编写,rtl风格,流水线设计,实现图像rgb格式到yuv格式的转换。-Verilog prepared, rtl style, pipeline design, realize image rgb to yuv format format conversion.
Date : 2025-12-21 Size : 1kb User : 苗苗

68013的USB通讯测试程序,具有两个批量管道,接收上位机指令并向其传输正弦波数据,用于USB开发中的测试。供参考。-68,013 of the USB communications test procedure, with two-volume pipeline to receive instructions to his PC data transmission sinusoidal for USB development testing. For reference.
Date : 2025-12-21 Size : 142kb User : 中银飞絮

该文档提出了一种应用于开关电容流水线模数转换器的CMoS预运放一锁存比较 器.该比较器采用UMC混合/射频0.18肛m 1P6M P衬底双阱CMOS工艺设计,工作电压为 1.8 V.该比较器的灵敏度为0.215 mV,最大失调电压为12 mV,差分输入动态范围为1.8 V,分辨率为8位,在40 M的工作频率下,功耗仅为24.4 ttW.基于0.18 gm工艺的仿真结 果验证了比较器设计的有效性.-A CMOS preamplifier-latch comparator used in switched··capacitor pipeline analog··to-digital con·- verter WBS presented.The comparator WaS d髑igned under UMC Mixed.Mode/RF 0.18 btm 1P6M P.Sub Twin— Well CMOS process and worked with 1.8V power supply.The sensitivity of the comparator was 0.215 mV, the largest offset voltage was 12 mV,the differentiaI input range Was 1.8 V,the resolution was 8 bit and the power dissipation Was only 24.4 gW at 40 MHz.HSPICE simulations of the comparator implemented in a 0.18 um technology demonstrate its effectiveness.
Date : 2025-12-21 Size : 353kb User : 赵恒

本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令,解决了大部分数据相关,结构相关,乘除法的流水化处理等问题,并实现了可屏蔽的中断网络。-This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly used to solve most of the data related to the structure related to the water processing multiplication and division problems, and realize the network that can shield the interrupt.
Date : 2025-12-21 Size : 91kb User : 李敏

管道写的简单的聊天室系统,编译通过,学习用-Pipeline write a simple chat room system, compile and study with
Date : 2025-12-21 Size : 1kb User : 孙旭勃
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