Search - fpga ram

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[Other Embeded program] epp_sram DL : 0: verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中，然后pc发送中断信号打断写过程读取sram中的数据。rar包中包含epp协议，模块文件和测试文件（test）。-Verilog FPGA code languages. Pc machine functions through a number of epp constantly write to the SRAM, and then pc send interrupt signals to interrupt the process of writing to read the data in the SRAM. rar package includes epp agreement, modules and test documents (test).
Date : 2025-12-22 Size : 42kb User : 苗苗
[Other Embeded program] ip DL : 0: usart的verilog代码.rar 包括很多的FPGA ip 源码，可以直接应用 uart_vhdl.zip sl811usb包含源程序.rar mc8051_design.zip mcpu_1[1].05.zip minicpu.zip mmc_lark_original.zip -USART the Verilog code. rar, including many of the FPGA ip source, can be applied directly uart_vhdl.zipsl811usb contains the source code. rarmc8051_design.zipmcpu_1 [1] .05. zipminicpu.zipmmc_lark_original.zip
Date : 2025-12-22 Size : 5.14mb User : 钟阳
[Other Embeded program] DDram DL : 0: 07全国大学生电子设计竞赛C题获奖作品FPGA外围接口双口RAM部分源码-07 National Undergraduate Electronic Design Contest winning entries C title peripheral interface FPGA dual-port RAM part of source
Date : 2025-12-22 Size : 1kb User : SRY
[Other Embeded program] ARM-read-FPGA-data1.7 DL : 0: ARM读取从FPGA双口RAM读取AD采样1.7-ARM FPGA dual-port RAM read to read from the AD sample 1.7
Date : 2025-12-22 Size : 1.3mb User : 张鹏
[Other Embeded program] The-pulse-signal-generator DL : 0: 脉冲信号发生器：采用DDS技术实现脉冲信号的周期、脉冲宽度、幅值的数控调节。通过单片机与FPGA的并行通信技术将频率控制字及矩形脉冲数据传送给FPGA的双口RAM。模拟输出通道则将信号通过100MHz、8位D/A转换器将波形数据转换成模拟脉冲信号，最后通过高速运放构成的放大器放大，实现幅度连续可调。-The pulse signal generator: using the DDS technology to achieve the pulse signal cycles, pulse width and amplitude of the numerical control regulation. Through the microcontroller and FPGA parallel communications will frequency control characters and rectangular pulse data to the FPGA double mouth RAM. Analog output channel will signal through 100MHz, eight D/A converter will waveforms converted into analog pulse signal, finally through high-speed op-amp constitute the amplifier amplification, realize the continuous adjustable range.
Date : 2025-12-22 Size : 19kb User : 张节
[Other Embeded program] ram DL : 0: 此代码可以是FPGA内部ram存储器在读取一系列数据后，然后每间隔1秒钟读出来。-This code can be read in the FPGA internal ram memory after a series of data, and then read out at intervals of 1 second.
Date : 2025-12-22 Size : 4.66mb User : 相猛唐