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[VHDL-FPGA-Verilog] traffic_1112 DL : 0: 一个交通灯的vhdl语言实现用ＶＣ的　　１．在指定的文件夹内查找某个文件　　　　　２．获取系统文件夹的路径，要求显示windows system temp 当前目录的路径Ｃ语言　　跳马问题：在５＊５的棋盘上，以编号为１的点出发，按日只跳马，要求不重复地跳所有位置，求出符合规则所有跳马的方案　　　　１　　６　　１５　　１０　　２１　　　　１４　９　　２０　　５　　　１６　　　　１９　２　　７　　　２２　　１１　　　　８　　１３　２４　　１７　　４　　　　２５　１８　３　　　１２　　２３ -a traffic light VHDL language of a VC. The designated folders to search within a document 2. Access to the system folder path, requested that the current windows system temp directory path C language vault : 5* 5 in the chessboard to the No. 1 starting point, the only daily vault and asked not to repeat all locations to jump to get in line with all rules of the program vault 1 6 15 10 21 14 9 20 5 16 19 2 7 22 11 8 13 24 17 4 25 18 3 12 23
Date : 2025-12-22 Size : 1kb User : 小三
[VHDL-FPGA-Verilog] RS232 DL : 0: （6）实验6：串口通讯实验，完整的设计工程文件在RS232文件夹下二、运行环境程序在以下环境调试通过：（1）Windows XP；（2）Altera公司的Quartus II 8.0 for windows；（3）Altera公司的Nios II 8.0 IDE for windows；（4）Mentor公司的ModelSim SE 6.0；-(6) (2) Altera Corporation Quartus II 8.0 for windows Experiment 6: serial communication experiment, a complete design engineering documents RS232 file folder Second, the operating environment program in the following environment debugging through: (1) Windows XP ( Company 3) Altera Nios II 8.0 IDE for windows (4) Mentor ModelSim SE 6.0
Date : 2025-12-22 Size : 13.46mb User : boyzone
[VHDL-FPGA-Verilog] ATA DL : 0: 能够完成硬件数据传输,包括PIO传输、MDMA传输、UDMA传输。程序设计是基于Windows协议，支持PIO传输，由2个block组成。-Able to complete the hardware data transmission, including PIO transfers, MDMA transmission, UDMA transfer. Program design is based on Windows protocol that supports PIO transfers by two block components.
Date : 2025-12-22 Size : 1.28mb User : 陈
[VHDL-FPGA-Verilog] nyhrf DL : 0: It has a wealth of parameter options, Dual-line interpolation FFT harmonic analysis kaiser windows, matlab wavelet analysis program.
Date : 2025-12-22 Size : 5kb User : fanlaopenben
[VHDL-FPGA-Verilog] ie156 DL : 0: Dual-line interpolation FFT harmonic analysis kaiser windows, Phased array antenna pattern (Chebyshev weights), Power System Transient Stability Program, can be transient stability.
Date : 2025-12-22 Size : 8kb User : yingkoufengging
[VHDL-FPGA-Verilog] galblas1 DL : 0: gal program loader for windows with description for galblaster board
Date : 2025-12-22 Size : 518kb User : mbuczek