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[VHDL-FPGA-Verilog] jtag0 DL : 0: 本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!-vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!
Date : 2025-12-26 Size : 84kb User : 马斌
[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码 DL : 0: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Date : 2025-12-26 Size : 416kb User : ken
[VHDL-FPGA-Verilog] usbsample DL : 0: 基于fpga和xinlinx ise的usb端口vhdl程序，希望对你有所帮助！-VHDL program for USB port based fpga and xinlinx ise, wish help for you!
Date : 2025-12-26 Size : 960kb User : 王萌
[VHDL-FPGA-Verilog] USB接口控制器参考设计_xilinx提供_vhdl DL : 0: USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code
Date : 2025-12-26 Size : 450kb User : 陈旭
[VHDL-FPGA-Verilog] USB控制器VHDL程序 DL : 0: USB控制器VHDL程（usb_xilinx_vhdl）,用XILINX公司的FPGA实现-VHDL-USB controller (usb_xilinx_vhdl) XILINX FPGA
Date : 2025-12-26 Size : 59kb User : 夏社
[VHDL-FPGA-Verilog] USB IPcore（带说明） DL : 0: USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
Date : 2025-12-26 Size : 399kb User : 陈友荣
[VHDL-FPGA-Verilog] ev-usbSIE DL : 0: ev-usbSIE　VHDL编写的USB程序-ev-usbSIE VHDL procedures prepared by the USB
Date : 2025-12-26 Size : 59kb User : 蒋谦
[VHDL-FPGA-Verilog] usb_xilinx_vhdl DL : 0: usb源码_xilinx_vhdl 这是Xilinx FPGA上的usb源码（VHDL)-usb-source _xilinx_vhdl This is a Xilinx FPGA on the usb source code (VHDL)
Date : 2025-12-26 Size : 55kb User : nanotalk
[VHDL-FPGA-Verilog] usb DL : 0: 这是个USB 的VHDL 程序，进去直接双击ISE 就可以用了-This is a USB-VHDL procedures, into direct ISE can use double-click the
Date : 2025-12-26 Size : 1.57mb User : 张亚伟
[VHDL-FPGA-Verilog] usb DL : 0: usb 硬件实现请大家多多指教-usb hardware realize the exhibitions please everyone
Date : 2025-12-26 Size : 2.19mb User : qqq
[VHDL-FPGA-Verilog] USB DL : 0: USB源代码，基于VHDL语言编写，在QuartusII上面已验证其功能-USB source code, based on the VHDL language, verified in QuartusII above its function
Date : 2025-12-26 Size : 5kb User : 周
[VHDL-FPGA-Verilog] USB DL : 0: 用VHDL实现的USB IP核，大家可以参考下-Use VHDL to achieve USB IP core, we can refer to the following
Date : 2025-12-26 Size : 1.09mb User : 蔡飞
[VHDL-FPGA-Verilog] USB DL : 0: USB通信协议的硬件描述语言代码，用于FPGA的总线接口控制器开发-USB communication protocol of the hardware description language code for the FPGA bus interface controller development
Date : 2025-12-26 Size : 137kb User : shigengxin
[VHDL-FPGA-Verilog] usb-blaster DL : 0: quartus多种USB-bletera 自制下载线！
Date : 2025-12-26 Size : 2.22mb User : 陈长佳
[VHDL-FPGA-Verilog] USB DL : 0: USB的VHDL实现源码（使用VHDL硬件描述语言，通过Altera QuartusII 开发）-USB to achieve the VHDL source code (using VHDL hardware description language, through the development of Altera QuartusII)
Date : 2025-12-26 Size : 49kb User : 刘磊
[VHDL-FPGA-Verilog] USB DL : 0: Verilog实现的USB程序，用ISE打开工程文件即可-Verilog implementation USB program, open the project file with the ISE can be
Date : 2025-12-26 Size : 137kb User : Roy
[VHDL-FPGA-Verilog] Usb DL : 0: 基于FPGA的驱动设计，使得用户的USB驱动在此完美实现。-FPGA-based drive design makes the user' s USB drive in this work perfectly.
Date : 2025-12-26 Size : 752kb User : liuyu
[VHDL-FPGA-Verilog] USB DL : 0: 用VHDL编写实现的USB接口控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the USB interface controller, bring their own testbench, after decompression project file can be opened with the ISE.
Date : 2025-12-26 Size : 153kb User : 陈阳
[VHDL-FPGA-Verilog] usb DL : 0: 程序说明: 本次实验控制开发板USB，与PC机进行通信，并在显示字符。目录说明: 工程在\project文件夹里面源文件和管脚分配在\rtl文件夹里面下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Note: In this experiment, control development board USB, and PC, to communicate, and display character. Catalog Description: The project \ project folder inside the source file and pins distributed in \ rtl folder inside download the file in the \ download folder inside,. Mcs for the PROM mode download files,. Bit for the JTAG debug download the file.
Date : 2025-12-26 Size : 79kb User : 军军
[VHDL-FPGA-Verilog] USB DL : 0: USB CY7C68013 键盘发送 VHDL FPGA-USB CY7C68013 keypad VHDL FPGA
Date : 2025-12-26 Size : 1.19mb User : 旧娃娃

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