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[VHDL-FPGA-Verilog] sdram_vhd_134 DL : 0: Xilinx Sdram控制器VHDL源代码-Sound code of Xilinx Sdram Controller based on VHDL
Date : 2026-01-10 Size : 53kb User : 刘汉忠
[VHDL-FPGA-Verilog] sdram_vhdl_lattice DL : 0: lattice sdram 控制器VHDL源代码-Sound code of Lattice Sdram Controller based on VHDL
Date : 2026-01-10 Size : 176kb User : 刘汉忠
[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Date : 2026-01-10 Size : 1007kb User : 包盛花
[VHDL-FPGA-Verilog] Verilog&Vhdl混语言对SDRAM的控制源代码 DL : 0: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Date : 2026-01-10 Size : 244kb User : 飞扬
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Date : 2026-01-10 Size : 758kb User : 张涛
[VHDL-FPGA-Verilog] sdr sdram controller DL : 0: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Date : 2026-01-10 Size : 2.34mb User : 陈东平
[VHDL-FPGA-Verilog] EvsStore DL : 0: 用VHDL编写的由FPGA控制SDRAM的存储控制程序-VHDL prepared by the FPGA control SDRAM memory control procedures
Date : 2026-01-10 Size : 1kb User :
[VHDL-FPGA-Verilog] sdramusevhdl DL : 0: sdram的vhdl实现本文介绍了sdram的控制时序特征，并介绍了采用vhdl语言实现的sdram控制器的关键技术-SDRAM This paper introduces the realization of SDRAM timing control features, and introduces the VHDL language SDRAM controller of the key technologies
Date : 2026-01-10 Size : 83kb User : cxr
[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl DL : 0: ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users.
Date : 2026-01-10 Size : 13kb User : hxwf801
[VHDL-FPGA-Verilog] sdram_control DL : 0: 这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
Date : 2026-01-10 Size : 332kb User : 李伟
[VHDL-FPGA-Verilog] SDRAM_HY57V6416ET DL : 0: 现代的4bank*1M*16bit的SDRAM（HY57V6416ET）的VHDL行为仿真程序-modern 4bank 1M** 16bit of SDRAM (HY57V6416ET) VHDL simulation program acts
Date : 2026-01-10 Size : 14kb User : 王森
[VHDL-FPGA-Verilog] sdram_inf DL : 0: sdram操作的vhdl源代码，对自己编写SDRAM核有很好的参考意义-SDRAM operation of VHDL source code, the preparation of their own nuclear SDRAM have a good reference value
Date : 2026-01-10 Size : 2kb User : 宋军
[VHDL-FPGA-Verilog] SDRAM DL : 0: 基于FPGA的SDRAM控制器的设计和实现,还比较好勒.-FPGA-based SDRAM controller design and realization, but also better le.
Date : 2026-01-10 Size : 68kb User : rubyshirial
[VHDL-FPGA-Verilog] sdram DL : 0: sdram test controller altera -sdram test controller altera
Date : 2026-01-10 Size : 1.45mb User : yangchun
[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog DL : 0: SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
Date : 2026-01-10 Size : 701kb User : 吴厚航
[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
Date : 2026-01-10 Size : 1007kb User : wfs
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: 基于VHDL编写的SDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller
Date : 2026-01-10 Size : 990kb User : wfs
[VHDL-FPGA-Verilog] vga_core(vhdl) DL : 0: vga视频输出（vhdl），主要是从sdram中产生图形，输出到vga中-vga video outputs [vhdl], mainly arising from the SDRAM graphics, output to vga Medium
Date : 2026-01-10 Size : 449kb User : 程荣
[VHDL-FPGA-Verilog] sdram DL : 0: 程序说明: 本次实验控制开发板上面的SDRAM完成读写功能。先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。 part1是使用Modelsim仿真的工程 part2是在开发斑上面验证的工程目录说明: part1: part1_32是4m32SDRAM的仿真工程 part1_16是4m16SDRAM的仿真工程 \model文件夹里面是仿真模型 \rtl文件夹里面是源文件 \sim文件夹里面是仿真工程 \test_bench文件夹里面是测试文件 \wave文件夹里面是仿真波形 -Procedure Note: In this experiment, control development board to complete the above SDRAM read and write capabilities. SDRAM write data inside first and then read out the data to compare, if you do not match on the adoption of LED variable light display, if agreed, LED does not light. part1 is to use Modelsim simulation project part2 the top spot verification in the development of the project directory Description: part1: part1_32 is 4m32SDRAM simulation project part1_16 is 4m16SDRAM simulation works \ model folder, which is a simulation model \ rtl folder, which is the source file \ sim is a simulation project inside the folder \ test_bench folder which is a test file \ wave inside the folder is a simulation waveform
Date : 2026-01-10 Size : 761kb User : 军军
[VHDL-FPGA-Verilog] sdram-source DL : 0: SDR SDRAM 控制器的源代码 altera公司的-source code from altera
Date : 2026-01-10 Size : 701kb User : wela

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