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[VHDL-FPGA-Verilog] anjian DL : 0: 按键输入模块（key）： --可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型 --前端模块：消抖 --对i0－i9十个输入端的两点要求： --（1）输入端要保证一段时间的稳定高电平 --（2）不能同时按下两个或多于两个的键 --后级模块：1、编码；2、可变模计数器 --编码模块：8线－4线（0－8 BCD码） --可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) :-- programmable delay generator (digital synchronous machine) the front-end input module : 0-2-9 10 numeric keys keys input module prototype-- front-end module : Consumers quiver-- the domain-Makes 10 input of the two requirements :-- (a) input to ensure a period of stability to I-- (2) can not be pressed together two or more two keys-- after class modules : one, coding; 2, variable Die counter-- Coding modules : 8-to-four (0-8 BCD)-- Variable Mode counter modules : coding module output to the 32 BCD value to Die
Date : 2026-01-10 Size : 2kb User : 汪汪
[VHDL-FPGA-Verilog] primetime DL : 0: 这是ＶＨＤＬ语言编写的延时测试程序，用来测定ＣＰＬＤ的性能指标-This is the VHDL language delay the test procedure used to determine the performance CPLD
Date : 2026-01-10 Size : 51kb User : 张国梁
[VHDL-FPGA-Verilog] yiwei DL : 0: 跑马灯-是移位寄存器有6个灯，无延时entity-Bomadeng-shift register is a six lights, without delay entity
Date : 2026-01-10 Size : 1kb User : 123
[VHDL-FPGA-Verilog] DELAY1 DL : 0: 本程序以ISE为开发平台，采用VHDL为开发语言，实现了对一个时钟信号延时的功能-the procedures to ISE for the development platform for the development of VHDL language, Implementation of a clock signal delay function
Date : 2026-01-10 Size : 1.26mb User : 刘小军
[VHDL-FPGA-Verilog] FPGAdesignXilinx DL : 0: 华为内部资料，关于FPGA设计的详细过程介绍，很不错的。本文档从FPGA器件结构出发以速度路径延时大小和面积资源占用率为主题描述在FPGA设计过程中应当注意的问题和可以采用的设计技巧。-Huawei internal information, with regard to detailed FPGA design process of introduction, it is good. This document from the FPGA device structure in order to speed the path delay and area the size of the theme of the occupancy rate of resource description in the FPGA design process should pay attention to the problems and design techniques can be used.
Date : 2026-01-10 Size : 1.63mb User : 高超
[VHDL-FPGA-Verilog] diantikongzhiqi DL : 0: 本设计是本人的课程设计，基于VHDL的电梯控制器的设计，能够实现12层电梯控制，上下开关，关门延时，提前关门，状态显示，通过波形仿真进行观看结果-The design is my curriculum design, VHDL-based elevator controller design, can achieve 12-storey elevator control, up and down switch, closing delay, early closing, the status display, through to watch the results of waveform simulation
Date : 2026-01-10 Size : 67kb User : polly
[VHDL-FPGA-Verilog] fft_statemachine DL : 0: FFT程序，此程序虽然耗逻辑资源很大，但是在接受数据后的第7个时钟沿就可以输出FFT变换后的数据，对要求时延较低的系统可以考虑-FFT procedure, this procedure should not consume a lot of logic resources, but the data in the first seven clock can be output along the FFT transformed data, the requirements of time-delay system can be considered lower
Date : 2026-01-10 Size : 7kb User : xiaoyuer
[VHDL-FPGA-Verilog] DDR_SDRAM_controller DL : 0: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Date : 2026-01-10 Size : 129kb User : xbl
[VHDL-FPGA-Verilog] delay DL : 0: 用vhdl的状态机实现精确的1us的延时程序-VHDL state machine used to achieve precise 1us delay procedures
Date : 2026-01-10 Size : 1kb User : yim
[VHDL-FPGA-Verilog] QuartusIIandModelSim DL : 0: 本文主要描述了如何在QUARTUS II 中输入程序文件，生成网表及标准延时文件，然后通过 MODELSIM进行功能仿真与后仿真的过程，主要为图解，含全部代码及仿真波形。 -This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation and post-simulation process, mainly for the diagrams, containing all the code and the simulation waveform.
Date : 2026-01-10 Size : 271kb User : 朱雯
[VHDL-FPGA-Verilog] lbuff_mem DL : 0: 延时代码,可以用在ＦＰＧＡ数据流水处理，图象处理，滤波-delay code
Date : 2026-01-10 Size : 2kb User : hungmin
[VHDL-FPGA-Verilog] BusDelay DL : 0: buffer delay vhdl model
Date : 2026-01-10 Size : 1kb User : gnomix
[VHDL-FPGA-Verilog] del_ctrl DL : 0: A VHDL logical example of memory delay controller -A VHDL logical example of memory delay controller
Date : 2026-01-10 Size : 1kb User : gios78
[VHDL-FPGA-Verilog] 2 DL : 0: FPGA设计中几个基本问题的分析及解决多时钟系统，时钟设计，时钟歪斜，门控时钟，毛刺信号及其消除，FPGA中的延时设计，FPGA设计应注意的其它问题-FPGA design analysis of a few basic questions and solve multi-clock system, clock design, clock skew, clock gating, and the elimination of burr signal, FPGA design of the delay, FPGA design should pay attention to other issues
Date : 2026-01-10 Size : 47kb User : 江凯
[VHDL-FPGA-Verilog] vhdlyanshi DL : 0: 关于vhdl语言中的延时处理，适合初学者查看，非常不错的例子，顶一下呀-With regard to the delay in vhdl language processing, suitable for beginners view, a very good example of what you Top
Date : 2026-01-10 Size : 146kb User : lishaozhe
[VHDL-FPGA-Verilog] LMS_filter DL : 0: verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
Date : 2026-01-10 Size : 342kb User : rayax
[VHDL-FPGA-Verilog] wtut_sc DL : 0: DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specified time (ps) of each other.
Date : 2026-01-10 Size : 104kb User : shad
[VHDL-FPGA-Verilog] vhdl-pdelay DL : 0: programmable delay register (16-bit) in VHDL source code
Date : 2026-01-10 Size : 81kb User : bfuclin
[VHDL-FPGA-Verilog] delay DL : 0: 短小易用的时序延迟程序，适用于Xilinx公司的FPGA产品-delay.vhd for Xilinx FPGA
Date : 2026-01-10 Size : 1kb User : xhnhd
[VHDL-FPGA-Verilog] vhdl-delay DL : 0: vhdl延时程序,源程序，已调试，可以用-VHDL delay program
Date : 2026-01-10 Size : 1kb User : 任贤齐

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